- AMD has begun using a 90-nm SOI manufacturing process at its Fab30
in Dresden, Germany
-
90-nm AMD64 is in active pilot mode in Fab 30 and prototype parts are
running in systems.
-
90-nm process would come in with all the advanced features acquired during
previous generations; including copper interconnect, a Black Diamond low-k
technology, and as an SOI process with the base wafers provided by Soitec SA.
-
The move to 90-nm has reduced the die size to 114 square millimeters,
about 40 percent of the die area compared with the established 130-nm process,
with reference to an Opteron prototype
-
The use of SOI at the 130-nm process node had reduced processor power
consumption to the 45-W to 55-W mark and that the shrink to 90-nm would produce
an additional benefit
-
Increasing the speed of the embedded memory controller and reducing the
latency in the HyperTransport technology
-
90-nm process started with a nine-layer interconnect back-end to match the
130-nm process to allow easy transition of established products, but that for
new or re-laid products the process could be extended to 11 layers.
-
AMD expects commercial shipment of products made using the 90-nm process
to begin in the third quarter.
-
300-mm wafer processing now expected early in 2006.
-
Strained-silicon would be introduced by AMD at some point in the future.
-
There are no plans to migrate the classic Athlon to 90-nm

- AMD has begun using a 90-nm SOI manufacturing process at its Fab30
in Dresden, Germany
-
90-nm AMD64 is in active pilot mode in Fab 30 and prototype parts are
running in systems.
-
90-nm process would come in with all the advanced features acquired during
previous generations; including copper interconnect, a Black Diamond low-k
technology, and as an SOI process with the base wafers provided by Soitec SA.
-
The move to 90-nm has reduced the die size to 114 square millimeters,
about 40 percent of the die area compared with the established 130-nm process,
with reference to an Opteron prototype
-
The use of SOI at the 130-nm process node had reduced processor power
consumption to the 45-W to 55-W mark and that the shrink to 90-nm would produce
an additional benefit
-
Increasing the speed of the embedded memory controller and reducing the
latency in the HyperTransport technology
-
90-nm process started with a nine-layer interconnect back-end to match the
130-nm process to allow easy transition of established products, but that for
new or re-laid products the process could be extended to 11 layers.
-
AMD expects commercial shipment of products made using the 90-nm process
to begin in the third quarter.
-
300-mm wafer processing now expected early in 2006.
-
Strained-silicon would be introduced by AMD at some point in the future.
-
There are no plans to migrate the classic Athlon to 90-nm