AMD is expected to announce a new dual-core, dual-processor platform later Thursday, in an attempt to roll over the competition in the enthusiast computing space. Dubbed “4×4″, the new enthusiast platform will debut at AMD’s Technology Day in its headquarters in Sunnyvale, Calif. Two Taiwan ODM system makers will launch 4×4 systems beginning in the second half of 2006. Each socket will include an AMD Athlon64 X2 chip in a new AM2 socket and will be connected using AMD’s “Direct Connect” architecture. Due to the nature of the Direct Connect architecture, each CPU can access the other’s dedicated memory store. The 4×4 board will also tweak the front-side bus speed. The 4×4 architecture will use unbuffered, non-ECC DIMMs and AMD’s “Pacifica” virtualization technology. Expect a really unique cooling solution. Part of the reason that AMD designed the multi-socket, multi-CPU 4×4 designs was that software manufacturers are starting to add threads, streams of software instructions that can be divvied up and processed separately by the individual CPUs.

AMD is expected to announce a new dual-core, dual-processor platform later Thursday, in an attempt to roll over the competition in the enthusiast computing space. Dubbed “4×4″, the new enthusiast platform will debut at AMD’s Technology Day in its headquarters in Sunnyvale, Calif. Two Taiwan ODM system makers will launch 4×4 systems beginning in the second half of 2006. Each socket will include an AMD Athlon64 X2 chip in a new AM2 socket and will be connected using AMD’s “Direct Connect” architecture. Due to the nature of the Direct Connect architecture, each CPU can access the other’s dedicated memory store. The 4×4 board will also tweak the front-side bus speed. The 4×4 architecture will use unbuffered, non-ECC DIMMs and AMD’s “Pacifica” virtualization technology. Expect a really unique cooling solution. Part of the reason that AMD designed the multi-socket, multi-CPU 4×4 designs was that software manufacturers are starting to add threads, streams of software instructions that can be divvied up and processed separately by the individual CPUs.