AMD has confirmed that the higher latencies are the result of provisions built into its 65nm processors for larger L2 cache sizes. They are quick to emphasize that this revelation is not tantamount to a product announcement, but the provisions are there should they decided to release such a product. The relatively small reduction in die area from 90nm to 65nm is not the result of added L2 cache being placed into silicon and then deactivated in the 4800+ and 5000+ models. Instead, the modest reduction in die size has origins in the esoterica of process technology and AMD’s model of continuous, gradual improvement to its manufacturing techniques.

AMD has confirmed that the higher latencies are the result of provisions built into its 65nm processors for larger L2 cache sizes. They are quick to emphasize that this revelation is not tantamount to a product announcement, but the provisions are there should they decided to release such a product. The relatively small reduction in die area from 90nm to 65nm is not the result of added L2 cache being placed into silicon and then deactivated in the 4800+ and 5000+ models. Instead, the modest reduction in die size has origins in the esoterica of process technology and AMD’s model of continuous, gradual improvement to its manufacturing techniques.