AMD is going to release the 90nm AMD64 processors soon for mobile, desktop
and servers and these are based on Revision D cores. According to some docs we
have seen, there is another major silicon revision change on the AMD64
processors taking place next year with Revision E. Rev E changes will be
affecting all the desktop and mobile Athlon 64 and Opteron processors.

Interestingly, Rev E will have Dual Core support for both 940 and 939-pin
processors. The 940-pin for server supports up to 8 registered DDR400 while the
939-pin for client supports up to 4 unbuffered DDR400. The Dual core has up to
1MB L2 cache per CPU, up to 3 HT link operating at 1Ghz max and a shared
northbridge registers with one APIC per core.

Rev E has better mismatched DIMM support and has 2-beat DRAM timing for
939-pin processors. Rev E also includes better power management features and an
enhanced DRAM controller. Indeed, Rev E will come with SSE-3 support with 11 of
out 13 instructions present in Prescott excluding MONITOR and MWAIT. Other
improvements include improved HyperTransport bandwidth for 940-pin at 2GT/s,
Adaptive Prefetch to optimize cache hit rate, two additional write-combining
buffers (total 4), XOR DRAM bank address to prevents page-thrashing on cache
write-backs and an expanded clock ramp hysteresis counter.

AMD is going to release the 90nm AMD64 processors soon for mobile, desktop
and servers and these are based on Revision D cores. According to some docs we
have seen, there is another major silicon revision change on the AMD64
processors taking place next year with Revision E. Rev E changes will be
affecting all the desktop and mobile Athlon 64 and Opteron processors.

Interestingly, Rev E will have Dual Core support for both 940 and 939-pin
processors. The 940-pin for server supports up to 8 registered DDR400 while the
939-pin for client supports up to 4 unbuffered DDR400. The Dual core has up to
1MB L2 cache per CPU, up to 3 HT link operating at 1Ghz max and a shared
northbridge registers with one APIC per core.

Rev E has better mismatched DIMM support and has 2-beat DRAM timing for
939-pin processors. Rev E also includes better power management features and an
enhanced DRAM controller. Indeed, Rev E will come with SSE-3 support with 11 of
out 13 instructions present in Prescott excluding MONITOR and MWAIT. Other
improvements include improved HyperTransport bandwidth for 940-pin at 2GT/s,
Adaptive Prefetch to optimize cache hit rate, two additional write-combining
buffers (total 4), XOR DRAM bank address to prevents page-thrashing on cache
write-backs and an expanded clock ramp hysteresis counter.