The new Star family includes quad-core Agena, mainstream dual-core Kuma, entry dual core Rana, and single-core Spica. The new Star microarchitecture has lots of improvements includes : Hyper-Transport 3.0 (from 2GT/s to 5.2GT/s), 32B Instruction Fetch, more precise Branch Prediction and Out-of-Order Load Execution, 4 Double Precision FLOPS/Cycle, Dual 128Bit SSE calculation, and Load per Cycle. AMD is persuading JEDEC to also put DDR2-1066 as the standard, letting the faster memory can be officially and natively supported in Star. Regarding with the 48 SSE4 to be added into Intel’s next-generation 45nm products, AMD has announced last week that Star will have SSE4A, a derivative edition of SSE4 in which those Intel 64 instructions are not available. Instructions include graphic, video encoding, 3D calculation, multimedia related are all compatible in Star.

The new Star family includes quad-core Agena, mainstream dual-core Kuma, entry dual core Rana, and single-core Spica. The new Star microarchitecture has lots of improvements includes : Hyper-Transport 3.0 (from 2GT/s to 5.2GT/s), 32B Instruction Fetch, more precise Branch Prediction and Out-of-Order Load Execution, 4 Double Precision FLOPS/Cycle, Dual 128Bit SSE calculation, and Load per Cycle. AMD is persuading JEDEC to also put DDR2-1066 as the standard, letting the faster memory can be officially and natively supported in Star. Regarding with the 48 SSE4 to be added into Intel’s next-generation 45nm products, AMD has announced last week that Star will have SSE4A, a derivative edition of SSE4 in which those Intel 64 instructions are not available. Instructions include graphic, video encoding, 3D calculation, multimedia related are all compatible in Star.