The energy efficiency of AMD chips increased tenfold over the last six years, but AMD thinks it can do much better.
Utilizing Heterogeneous System Architecture on chips is the key to massive increases in the power efficiency of AMD’s processors, according to AMD’s CTO Mark Papermaster.
Papermaster said this during a keynote Thursday at the China International Software and Information Service Fair conference in Dalain, China, where he outlined AMD’s plans to increase the power efficiency of AMD’s APU chips by 2020.
“Through APU architectural enhancements and intelligent power efficient techniques, our customers can expect to see us dramatically improve the energy efficiency of our processors during the next several years,” he said during his keynote. “Setting a goal to improve the energy efficiency of our processors 25 times by 2020 is a measure of our commitment and confidence in our approach.”
HSA, according to Papermaster, will help improve power efficiency because it will make the system more efficient overall from a computing perspective — each CPU and GPU cycle will be able to accomplish more allowing a slower clockspeed to offer better performance than before. AMD’s next step will be to develop hardware-based tools that can adjust clockspeeds and voltage based on the task at hand — which sounds a lot like MediaTek’s CorePilot — as well as develop hardware-level enhancements including “”inter-frame power gating, per-part adaptive voltage, voltage islands, [and] further integration of system components.”
In order for AMD to accomplish this feat, it says it will need to break the “natural” efficiency curve of Moore’s Law by 70 percent between 2014 and 2020.
Given the power efficiency and TDP issues with AMD’s current crop of silicon (see: Kaveri), the company certainly has its work cut out for it if it wants to reach this goal.