Intel plans to incorporate Execute Disable Bit (NX Bit) security technology
into Prescott-based Pentium 4 and Celeron D CPUs in Q3 this year. Only
LGA775-pin processors with E-0 stepping will initially have NX Bit support. The
letter “J” will be used after model numbers to distinguish chips incorporating
the new technology. Pentium M and Celeron M chips with NX Bit-support are
expected in the first quarter of 2005.










Processor Model

Processor Model
Number

Processor Speed

Jun ’04
Aug 22
Pentium 4
570J

3.8Ghz
 $ 640 (At Launch)

560J/560

3.6Ghz

$ 637
$ 417

550J/550

3.4Ghz

$ 417
$ 278

540J/540

3.2Ghz

$ 278
$ 218

530J/530

3.0Ghz

$ 218
$ 178

520J/520

2.8Ghz

$ 178
$ 165
Celeron D
340J/340

2.8Ghz

$ 178
$ 117

335J/335

2.8Ghz

$ 117

 $ 103

330J/330

2.66Ghz
$ 89
 $ 83

325J/325

2.53Ghz
$ 79
 $ 79

Intel plans to incorporate Execute Disable Bit (NX Bit) security technology
into Prescott-based Pentium 4 and Celeron D CPUs in Q3 this year. Only
LGA775-pin processors with E-0 stepping will initially have NX Bit support. The
letter “J” will be used after model numbers to distinguish chips incorporating
the new technology. Pentium M and Celeron M chips with NX Bit-support are
expected in the first quarter of 2005.













Processor Model

Processor Model Number

Processor Speed

Jun ’04
Aug 22
Pentium 4570J3.8Ghz $ 640 (At Launch)
560J/5603.6Ghz$ 637$ 417
550J/5503.4Ghz$ 417$ 278
540J/5403.2Ghz$ 278$ 218
530J/5303.0Ghz$ 218$ 178
520J/5202.8Ghz$ 178$ 165
Celeron D340J/3402.8Ghz$ 178$ 117
335J/3352.8Ghz$ 117 $ 103
330J/3302.66Ghz$ 89 $ 83
325J/3252.53Ghz$ 79 $ 79

Requirements

o The conversion to E-0 Step will incorporate power optimizations to enable
speed enhancements
o Includes Execute Disable Bit support and additional power management features
(LGA775 only)
o The CPU ID will change from 0xF34h to 0xF41h
o Updated BIOS required
o E-0 is pin compatible with D-0