Haswell-EP and Broadwell-EP Xeons on time: Intel server CPU gravy train speeds further
What does the future hold for the mainstream Xeon processor line? Will it face the roadmap uncertainties of off-the-shelf desktop CPUs for the next year or two?
Good news: Haswell-EP and Broadwell-EP Xeons are on time.
After a bit of slowdown that seems to have resulted from both lack of competition, and the teething troubles of the 22 and 14nm process, the next few rounds are proceeding at full speed.
Why such a change? After all, it’s not as if AMD seems to be getting back into the high-end field, to everyone’s disappointment (and no, they cannot blame anyone else but themselves). While ARM is nowhere as efficient as the old Alpha or MIPS were when it comes to high-compute jobs, the money power that ARM now sits on, supported by its rich and powerful vendors, does drool at the royal margins that Intel earns of its four-digit priced Xeons, compared to pitiful few bucks to few dozen dollars that ARM processors go for.
The heavyweights like Samsung, Huawei, Apple, Qualcomm and Nvidia, plus a number of ARM-specific niche CPU makers – AMD included – are trying to aim for this market.
Intel had a very successful Ivy Bridge Xeon-EP (officially known as Xeon E5-2600 v2) rollout this past quarter. Both the 8-core E5-2687Wv2 (3.4 GHz before Turbo, mind you), the main high end 10-core 3 GHz E5-2690v2, and the 12-core 2.7 GHz E5-2697v2, supposedly a cut-down 15-core Xeon E7v2, are all sold out – and these are just the highest-ASP SKUs. I’ve worked with few of these speed bins on various workstation and HPC loads, with both DDR3L-1600 and DDR3-1866 memory, and its cache and memory subsystems are so effective that the actual memory choice doesn’t seem to matter much in most benchmarks.
The next few months will keep them busy introducing the four-socket Xeon EP v2 versions, as well as multi-socket Xeon EX v2, the 15-core monsters with 37.5 MB L3 and triple QPI channels per socket, covered here before.
So, what comes after them?
As explained a year ago, Haswell-EP development was in full swing for quite a while, and the first round of engineering samples seems to run very well. Just like Ivy Bridge-EP, the Haswell EP, officially Xeon E5v3, will have multiple die flavours to address both low-core count but high MHz, and high core count at less MHz, for various workstation, server and supercomputer and big data workloads.
While the Ivy Bridge-EP had 6-core and 10-core dies, with the 12-core flavor borrowed from the EX line, the Haswell-EP will have 8-core and 14-core dies at least – where it’s not confirmed yet if the top core-count die is also “borrowed from the 16+ core Haswell-EX”, meaning there is again a separate say 12-core main line “native” Haswell EP. We’ll know soon, as the systems start sampling to the OEMs and critical users over the next few months. This round of sampling will take Intel a bit more validation care and effort, since many other new things like DDR4 memory, sped-up 9.6 GT/s QPI, native USB3, SAS12G and PCIe SSDs will be rolled out at the same time into these systems.
Assuming the clock rates stay similar to the current E5v2, the top end of the Xeon E5v3, when they officially surface likely at (or just before) the next Intel Fall IDF in San Francisco, will be able to achieve close to 700 GFLOPs in double precision FP per socket, or 1.4 TFLOPs for a typical dual socket board – something that any top end GPU would have hard time matching, and this is without esoteric CUDA or OpenCL coding.
Even the 8-core enthusiast desktop Haswell-E, Core i7 59xx, will be able to give close to half a teraflop in double precision without much overclocking – the FMA fused multiply add extras do help here, something that 64-bit MIPS architecture had for over 15 years now, by the way.
Then we come to 2015, the same year when the next Xeon Phi would come out. The Xeon CPU to match it in the middle of that year will be “Broadwell EP” Xeon E5 v4, the first high end Xeon to be made in 14nm process. How about up to 18 cores and 45 MB L3 per socket, coupled with even faster memory? How will its innovations impact the competition?
The second part of this two-part series will be published on December 17.