The HyperTransport Consortium is hiking up its throughput and
building bridges to the emerging PCI Express interconnect with a version 2.0.
The updated spec, available immediately, sports a 75 percent increase in data
handling. The new version will provide aggregate throughput up to 22.4 Gbytes/second
on a 32-bit wide bi-directional link using new speeds grades of 1.0, 1.2 and 1.4
GHz. That’s up from 12.8 Gbytes/s on the current spec typically running at 800
MHz. The new speed grades of version 2.0 deliver up to 2.0, 2.4 and 2.8
Gtransfers/s, up from 1.6Gtransfers/s. The new version carries over existing 2-,
8-, 16- and 32-bit widths. Computer CPUs from AMD will be the most likely parts
to need the boosted bandwidth first, although no consortium members provided any
details of their plans to support version 2.0.

HT 2.0 gets its speed boost through the use of signal
de-emphasis and a more sensitive receiver. By using these techniques and
avoiding more complex approaches such as dynamic phase alignment, the spec
requires relatively little hardware redesign and will not require parts that
consume more power. The new spec is backwards compatible with today’s
interconnect. Devices will come up in a 200 MHz version 1.0 mode and
auto-negotiate for the fastest speed they can support. Separately, version 2.0
includes an annex that defines a mapping of HyperTransport to the new 2.5-Gbit/s
PCI Express spec defined by a team led by Intel Corp. HyperTransport already
supports mappings to PCI and PCI-X. Companies including Alliance Semiconductor,
AMD and PLX Technologies make HyperTransport to PCI-X bridges.

HyperTransport™ Technology Consortium today announced a major
new release of the HyperTransport Technology I/O Link Specification. The
HyperTransport Release 2.0 Specification introduces three more powerful bus
speeds and mapping to PCI Express, an emerging I/O interconnect architecture.
HyperTransport’s speed capability extends from the 1.6 Giga Transfers/second (GT/s)
of Release 1.1 Specification to 2.0, 2.4, and 2.8 GT/s using dual-data rate
clocks at 1.0, 1.2, and 1.4 Gigahertz, delivering a maximum aggregate bandwidth
of 22.4 Gigabytes/second. The electrical protocols supporting the new clock
rates are backward compatible with all previous versions of the HyperTransport
electrical specifications.

"Our Release 2.0 Specification delivers the top performance expected by the
industry for its next generation computing, communications and embedded
platforms," said Mario Cavalli, General Manager of the HyperTransport Technology
Consortium. "Release 2.0′s substantial speed and bandwidth extensions combined
with PCI Express bus extensibility reaffirm and consolidate HyperTransport’s
long term chip-to-chip I/O technology leadership while preserving
HyperTransport’s low implementation cost and the multi-million dollars
investments made by the HyperTransport Consortium members and their considerable
customer base."

"These new specifications are in response to HyperTransport Consortium’s members
expectation of backward compatibility with Release 1.05 and Release 1.1
Specifications along with state-of-the-art performance," noted Brian Holden,
Chair of the Technical Working Group, responsible for the development of the
technical specification. "We achieved our goal of successfully increasing data
throughput without a major rework of the basic electrical specification."

"Release 2.0 Specification confirms the significant contribution that
HyperTransport has been making to the industry over recent years," said Gabriele
Sartori, President of the HyperTransport Technology Consortium. "Our technology
empowers leading edge products like Microsoft’s Xbox, Apple’s Power Mac G5,
Cisco’s high-end routers, IBM’s and Sun Microsystems’s servers, notebooks and
Tablet PC’s based on Transmeta’s Efficeon-processor, and all AMD’s Athlon64- and
Opteron-based PCs, servers and supercomputers."

"As the first of the high-bandwidth I/O technologies to reach volume shipments,
HyperTransport technology has already gained significant traction in the
industry," says Jim Turley, principal analyst at SiliconInsider. "It is a
further advantage for the HyperTransport-based industry to have a defined
roadmap to faster performance and clean mapping to emerging I/O links."

About HyperTransport™ Technology

HyperTransport chip-to-chip interconnect technology is a universal CPU to I/O
connection technology that replaces existing multi-level buses in systems such
as personal computers, servers, embedded architectures and high performance
appliances. It provides extremely high bandwidth, frequency scalability, low
implementation cost, and software compatibility with legacy Peripheral Component
Interconnect (PCI), PCI- and PCI Express technologies. HyperTransport technology
delivers state-of the-art bandwidth by means of easy-to-implement Low Voltage
Differential Signaling (LVDS)point-to-point links, delivering increased data
throughput while minimizing signal crosstalk and EMI. It employs a packet-based
data protocol to eliminate many sideband (control and command) signals and
supports asymmetric, variable width data paths.

HyperTransport technology is embedded in multiple CPU families from AMD,
Broadcom, PMC-Sierra and Transmeta and it has established a significant presence
in a number of key market sectors. It is licensed on a royalty-free basis by the
HyperTransport Technology Consortium. A full list of HyperTransport-based
products and HyperTransport Consortium’s member companies can be found at:

About the HyperTransport™ Technology Consortium

The HyperTransport Technology Consortium is a membership-based non-profit
organization in charge of managing and promoting HyperTransport Technology. It
consists of over 40 member companies, including promoter members Advanced Micro
Devices, Alliance Semiconductor, Apple Computer, Broadcom Corporation, Cisco
Systems, NVIDIA, PMC-Sierra, Sun Microsystems, and Transmeta. Membership is open
to any company interested in leveraging the HyperTransport technology. It is
based on a minimal yearly fee and includes the right to royalty-free use of
HyperTransport technology and Intellectual Property. More information can be
obtained at HyperTransport Technology Consortium’s website at

Consortium members have access to HyperTransport technical documents database
and may attend consortium meetings and events. To become a member, visit the
consortium web site at