The HyperTransport Consortium has unveiled optional upgrades
to its protocol specification to open the door to greater use of its
interconnect for handling data plane packet traffic in communications systems.
The 1.1 version of HyperTransport, called DirectPacket, includes four changes
the group expects to see some members support in silicon in the next six to 18
months. The key aspect of the HyperTransport upgrade is a native packet handling
mechanism that brings message passing semantics to what has been the
memory-mapped load/store architecture. The feature is implemented by reusing
low-level address bits, thus avoiding any additional protocol overhead for
packet handling.

Meanwhile, work continues in the consortium on a version 2.0
of the underlying physical layer of the spec, expected to “more than double” the
current 1.6 Gbits/second data rates of the interconnect. Preparing the way for
that spec, the new protocol upgrade also includes an error-retry protocol to
bolster error correction capabilities of HyperTransport. Intel is building
similar packet-handling and peer-to-peer routing capabilities into its emerging
Advanced Switching specification, a communications-centric variant of PCI
Express. However, in Intel’s case the work involves defining a new protocol for
the Express physical layer spec. The AS spec is not expected to be finished
until the end of this year.


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