IBM Doubled Frequency For Power6 CPU

IBM will go back to the future with its next-generation Power6 design by pushing raw speed rather than trying to pack more cores on a die.
The CPU will run at speeds between 4-5GHz with a total of 8Mbytes L2 cache and a 75Gbyte/second link to external memory. The Power6 doubles the frequency and bandwidth of the existing Power5 without increasing its power consumption or the depth of its execution pipeline. New circuit designs and process technology improvements plow the way for the advances. The chip uses new and highly complex latch and static gate circuits. The processor is built in a 65-nm process using IBM’s SOI and strained silicon technology. IBM applied new techniques in variable gate lengths and variable threshold voltages to squeeze maximum performance per Watt at the transistor level. The chip can be fully operated at as little as 0.8V. The move lets IBM ship the chip as a mid-2007 refresh for its existing p-series server line.


IBM will go back to the future with its next-generation Power6 design by pushing raw speed rather than trying to pack more cores on a die.
The CPU will run at speeds between 4-5GHz with a total of 8Mbytes L2 cache and a 75Gbyte/second link to external memory. The Power6 doubles the frequency and bandwidth of the existing Power5 without increasing its power consumption or the depth of its execution pipeline. New circuit designs and process technology improvements plow the way for the advances. The chip uses new and highly complex latch and static gate circuits. The processor is built in a 65-nm process using IBM’s SOI and strained silicon technology. IBM applied new techniques in variable gate lengths and variable threshold voltages to squeeze maximum performance per Watt at the transistor level. The chip can be fully operated at as little as 0.8V. The move lets IBM ship the chip as a mid-2007 refresh for its existing p-series server line.

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