IBM Dual Core PowerPC 970MP Info

IBM is readying a dual-core version of its PowerPC 970 processor, called the
PowerPC G5 by Apple. The new chip, code-named Antares will make its way into
workstations and servers sometime next year. IBM may start production of the
PowerPC 970MP in early 2005. The new dual-core version will be designated
PowerPC 970MP and will be available for testing purposes later this summer. The
PowerPC 970MP will contain two processing units per chip, with each carrying its
own execution core, Level 1 cache and storage subsystems including 1MB Level 2
cache. The new chip will let vendors scale up server lines to a four-way SMP
configuration.

Hardware and software optimizations would make PowerPC 970MP more efficient
in many computing situations than two separate processors at the same clock
speed. The 970MP will be deeply pipelined using 16 stages for most fixed-point
integer operations; 18 for most load-and-store operations; and 21 stages for
most floating-point operations. VMX operations, which will take 19 stages, will
be handled in the 970MP’s AltiVec-compatible vector processing unit. With the
longer pipelining, the 970MP will implement "instruction cracking," which can
distribute code requests to each core, splitting certain recognized instructions
into several internal and simpler operations.


IBM is readying a dual-core version of its PowerPC 970 processor, called the
PowerPC G5 by Apple. The new chip, code-named Antares will make its way into
workstations and servers sometime next year. IBM may start production of the
PowerPC 970MP in early 2005. The new dual-core version will be designated
PowerPC 970MP and will be available for testing purposes later this summer.

The PowerPC 970MP will contain two processing units per chip, with each
carrying its own execution core, Level 1 cache and storage subsystems including
1MB Level 2 cache. The new chip will let vendors scale up server lines to a
four-way SMP configuration. Hardware and software optimizations would make
PowerPC 970MP more efficient in many computing situations than two separate
processors at the same clock speed. The 970MP will be deeply pipelined using 16
stages for most fixed-point integer operations; 18 for most load-and-store
operations; and 21 stages for most floating-point operations. VMX operations,
which will take 19 stages, will be handled in the 970MP’s AltiVec-compatible
vector processing unit. With the longer pipelining, the 970MP will implement
"instruction cracking," which can distribute code requests to each core,
splitting certain recognized instructions into several internal and simpler
operations.

The 970MP processor cores will share a single EI (Elastic Interface) bus to
an external north-bridge memory interface. The bus supports multiple bus ratios,
from 2:1 to 24:1, giving manufacturers a range of options for matching processor
and memory speeds. The PowerPC 970MP will be a significantly larger package than
the existing PowerPC 970FX. The PowerPC 970MP will spread out over 154 square
millimeters. Though the PowerPC 970MP will feature a dozen power mode states
(Full Run, Doze, Nap and Deep Nap, at one of three throttle speed states), the
power and heat results for the dual-core model will be higher than for a
single-core PowerPC 970FX. Apple’s current dual-processor machines use a water
cooling technology and likely the dual-core machines will as well.

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