• Power6 can count to 10–and perform numerous other mathematical
    operations–with the decimal digits 0 through 9 rather than the binary digits
    of 0 and 1 used by conventional computers
  • Power6 incorporates the AltiVec also known as VMX instruction set speeds
    up many multimedia tasks. Tradeoff is the electrical current "leakage"
    problems in today’s chipmaking technology where even idle parts of a chip
    consume power and produce waste heat.
  • Power6 will run at speeds of 4GHz to 5GHz but will be closer to 5GHz than
    it is to 4GHz.
  • Power6 can transfer data on and off chip at 300GBps, twice of Power5
  • Moved some higher-end reliability features from its mainframe line to
    Power6
  • Each Power6 chip has 2 cores, and each core has 4MB of L2 compared with a
    2MB shared cache in Power5
  • Two cores can share an optional 32MB of level-three cache separate from
    the chip
  • Each core can simultaneously handle two instruction sequences, called
    "threads
  • To improve virtualization abilities, Power6 can be subdivided into as many
    as 1,024 separate partitions, each with its own operating system.
  • Power6 chip can connect directly to three others in four-socket groupings
    using a first-tier communication fabric. And each of those groupings can
    connect directly with seven others over a second-tier communication fabric.
    The two-tier fabric keeps all the processors’ cache memories synchronized

  • Power6 can count to 10–and perform numerous other mathematical
    operations–with the decimal digits 0 through 9 rather than the binary digits
    of 0 and 1 used by conventional computers
  • Power6 incorporates the AltiVec also known as VMX instruction set speeds
    up many multimedia tasks. Tradeoff is the electrical current "leakage"
    problems in today’s chipmaking technology where even idle parts of a chip
    consume power and produce waste heat.
  • Power6 will run at speeds of 4GHz to 5GHz but will be closer to 5GHz than
    it is to 4GHz.
  • Power6 can transfer data on and off chip at 300GBps, twice of Power5
  • Moved some higher-end reliability features from its mainframe line to
    Power6
  • Each Power6 chip has 2 cores, and each core has 4MB of L2 compared with a
    2MB shared cache in Power5
  • Two cores can share an optional 32MB of level-three cache separate from
    the chip
  • Each core can simultaneously handle two instruction sequences, called
    "threads
  • To improve virtualization abilities, Power6 can be subdivided into as many
    as 1,024 separate partitions, each with its own operating system.
  • Power6 chip can connect directly to three others in four-socket groupings
    using a first-tier communication fabric. And each of those groupings can
    connect directly with seven others over a second-tier communication fabric.
    The two-tier fabric keeps all the processors’ cache memories synchronized