Pentium M Architecture
Pentium M codenamed
Banias is based on 0.13 micron technology and has 77 million
1MB L2 cache and 32KB L1 cache.
Pentium M runs on a 400Mhz system bus uses Source-Synchronous
Transfer (SST) of address and data to improve performance by
transferring data four times per bus clock. As you can see from
above, the L2 cache is separated into 4 areas to allow power down
of unused L2 cache to conserve power. Pentium M will have SSE2
optimizations that include 128-bit SIMD ALU and 128-bit SIMD FP
like the Pentium 4 processors. Pentium M processor utilizes
socketable Micro Flip-Chip Pin Grid Array (Micro-FCPGA) and
surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA)
package technology. The Micro-FCPGA package plugs into a 479-hole,
surface-mount, Zero Insertion Force (ZIF) socket, which is
referred to as the mPGA479M socket.
Here are the some
technical marketing specs to help you understand better :
Advanced Branch Prediction
Uses advanced instruction
prediction that allows the processor to Analyzes a program’s past behavior
and predicts which operations it is likely to request in the
future. The processor can line up instructions for execution
before a program request them. If Pentium M processor can predict
the branches correctly, it will make it more efficiency thereby
Uses few CPU resources to execute
operations by merging CPU operations together prior to execution
in order to increase performance and efficiency. When micro-ops
are fused, they use less processor resources in order to handle
the same number of operations.
Dedicated Stack Management
Uses Dedicated Stack Manager in
done in hardware to keep
track of internal accounting, allowing the processor to execute
program instructions without interruption and uses less power.
Enhanced SpeedStep Technology (GeyserVille
This technology enables the
processor to switch between multiple frequency and voltage points
instead of two currently on Pentium 4-M based on SST. This will
enable superior performance with optimal power savings. The
processor features the Auto Halt, Stop-Grant, Deep Sleep, and
Deeper Sleep low power states.
- Multiple voltage/frequency
operating points provide optimal performance at the lowest
- Voltage/Frequency selection is
software controlled by writing to processor MSR’s (Model
Specific Registers) thus eliminating chipset dependency.
- If the target frequency is
higher than the current frequency, Vcc is ramped up by placing a
new value on the VID pins and the PLL then locks to the new
- If the target frequency is lower
than the current frequency, the PLL locks to the new frequency
and the Vcc is changed through the VID pin mechanism.
- Software transitions are
accepted at any time. If a previous transition is in progress,
the new transition is deferred until its completion.
- The processor controls voltage
ramp rates internally to ensure glitch free transitions.
- Low transition latency and large
number of transitions possible per second.
- Processor core (including L2
cache) is unavailable for up to 10 µs during the frequency
- The bus protocol (BNR#
mechanism) is used to block snooping
No bus master
arbiter disable required prior to transition and no processor
cache flush necessary.
Thermal Monitor mode. When the on-die thermal sensor indicates
that the die temperature is too high, the processor can
automatically perform a transition to a lower frequency/voltage
specified in a software programmable MSR. The processor waits
for a fixed time period. If the die temperature is down to
acceptable levels, an up transition to the previous
frequency/voltage point occurs. An interrupt is generated for
the up and down better system level thermal management.
Intel Pentium M processor 1.60GHz Core VCC for Enhanced
Intel SpeedStep® technology operating points:
Summary Table For
Pentium M Processors
Min. SST Clock
|LV Pentium M||1.10Ghz||1.18V||12W||600Mhz||0.96V||6W||< 1W|
|ULV Pentium M||900Mhz||1.00V||7W||600Mhz||0.85V||4W||< 1W|
Further Into The Roadmap
Further down the road, we can expect to
see Intel Pro/Wireless 2100A Dual Band version in Q2 while the Calexico2 supporting the
802.11g is expected to be released in Q1 2004. The next generation
90nm Pentium M codenamed Dothan is scheduled for release in Q4
this year and the voltage is lowered to 1.31V and TDP is lowered
to 21W and its supporting chipset 855GME will support DDR333
and faster graphics core engine of 250Mhz. The next generation
chipset for Pentium-M in H2 2004 will be PCI Express with
PCI Express x16 interface AGP bus and DDR-II SDRAM