Intel today announced that it has begun a $ 2 billion construction project to convert a 200mm wafer fabrication facility to a state-of-the-art 300mm facility in Chandler, Ariz. The conversion of Fab 12 is scheduled to be completed in late 2005. The converted facility will begin initial production on 65-nanometer process technology. When completed, the converted Fab 12 will become Intel’s fifth 300mm wafer facility. Five 300-mm fabs provide the equivalent manufacturing capacity of about 10 200mm factories. Intel’s other 300mm fabs are located in Hillsboro, Ore. (two facilities), Rio Rancho, N.M. and Leixlip, Ireland.

Intel today announced that it has begun a $ 2 billion construction project to
convert a 200mm wafer fabrication facility to a state-of-the-art 300mm facility
in Chandler, Ariz. The conversion of Fab 12 is scheduled to be completed in late
2005. The converted facility will begin initial production on 65-nanometer
process technology.

"This project represents a first for Intel — the first complete conversion of
an existing 200mm wafer fab to a 300mm fab," said Bob Baker, Intel senior vice
president and general manager, Technology and Manufacturing Group. "The
flexibility of our factory designs allows us to completely and efficiently
modify the interior of the cleanroom to accommodate the much larger 300mm
production equipment.

"This conversion will not only enable us to improve our capital efficiency by
giving us more than twice the capacity at significantly lower costs, but it will
enable us to utilize our experienced and talented workforce in Arizona."

When completed, the converted Fab 12 will become Intel’s fifth 300mm wafer
facility. Five 300-mm fabs provide the equivalent manufacturing capacity of
about 10 200mm factories. Intel’s other 300mm fabs are located in Hillsboro,
Ore. (two facilities), Rio Rancho, N.M. and Leixlip, Ireland. Wafers of 300mm
are approximately 12 inches in diameter, providing an increase in surface area
of 225 percent over more common 200mm wafers. This allows manufacturers to put
significantly more individual computer chips on a wafer, dramatically reducing
the cost of each chip. The bigger wafers also diminish the overall use of
resources, requiring 40 percent less energy and water for each chip produced.