The
Register
has an interesting piece of article on the Intel’s future direction
and plans on 80-cores or more chip and the upcoming CSI platforms. For the
80-core Polaris research chip, Intel’s researchers have been hammering away on
the concept of 3-D memory where the cache rests above the processor cores. This
technique lets a core anywhere on a single slice of silicon tap the cache in
just a couple of cycles rather than traversing the entire chip to reach the
cache bank. On the CSI platforms, they managed to spot one board code-named
Coalbrook or CoalCreek and another called Springville that had built-in optical
modules. Both systems were identified as using Intel’s upcoming CSI technology
which is the company’s attempt to catch-up to AMD’s Hypertransport/integrated
memory controller technology.

The
Register
has an interesting piece of article on the Intel’s future direction
and plans on 80-cores or more chip and the upcoming CSI platforms. For the
80-core Polaris research chip, Intel’s researchers have been hammering away on
the concept of 3-D memory where the cache rests above the processor cores. This
technique lets a core anywhere on a single slice of silicon tap the cache in
just a couple of cycles rather than traversing the entire chip to reach the
cache bank. On the CSI platforms, they managed to spot one board code-named
Coalbrook or CoalCreek and another called Springville that had built-in optical
modules. Both systems were identified as using Intel’s upcoming CSI technology
which is the company’s attempt to catch-up to AMD’s Hypertransport/integrated
memory controller technology.