Intel Demo Xeon MP Tigerton Server

Intel has demonstrated a server based on the upcoming quad-core Tigerton processors, part of its Xeon MP chip family in the third quarter of 2007. Servers based on Tigerton will use the Clarksboro chipset. Clarksboro eliminates the dual-independent bus structure used on current Tulsa-class servers and replaces it with a dedicated link between each quad-core chip and the chipset. Clarksboro will also introduce fully buffered memory to the MP lineup. An Intel engineer ran a SunGard financial modeling application on a preproduction server based using four Tigertons, each with four cores, for a total of 16 independent processing cores.


Intel has demonstrated a server based on the upcoming quad-core Tigerton processors, part of its Xeon MP chip family in the third quarter of 2007. Servers based on Tigerton will use the Clarksboro chipset. Clarksboro eliminates the dual-independent bus structure used on current Tulsa-class servers and replaces it with a dedicated link between each quad-core chip and the chipset. Clarksboro will also introduce fully buffered memory to the MP lineup. An Intel engineer ran a SunGard financial modeling application on a preproduction server based using four Tigertons, each with four cores, for a total of 16 independent processing cores.

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