Intel plans to embed a memory controller and to use a common high-speed
serial interconnect as the processor bus for its Itanium and Xeon server
processors starting in 2007. The so-called CSI interconnect will compete with
HyperTransport — the fast, low latency processor bus developed by AMD for their
K8 processors. The final specification for the interconnect is still being
hammered out by engineers working with the server CPU design teams. Intel’s CSI
bus will first appear on the Tukwila, a multi-core version of Intel Itanium CPU
set to ship in 2007. The CSI bus is also expected to appear in 2007 versions of
Intel’s x86 Xeon server CPUs, probably including the chip code-named Whitefield.

The CSI bus is optimized for low latency when used as a cache coherent
processor bus in four-processor systems. However, it can also be used to link up
to 16 CPUs for the high-end X86 systems built by OEMs such as IBM, NEC and
Unisys. In addition, CSI will be used without cache coherency as a standard way
to link north and south bridge chips in a processor core logic set. By using a
common interconnect as a chip-to-chip link, Intel will be able to develop
similar board-level designs and software tools for Itanium and Xeon systems.
That could reduce the costs of supporting the two server architectures.

Intel plans to embed a memory controller and to use a common high-speed
serial interconnect as the processor bus for its Itanium and Xeon server
processors starting in 2007. The so-called CSI interconnect will compete with
HyperTransport — the fast, low latency processor bus developed by AMD for their
K8 processors. The final specification for the interconnect is still being
hammered out by engineers working with the server CPU design teams. Intel’s CSI
bus will first appear on the Tukwila, a multi-core version of Intel Itanium CPU
set to ship in 2007. The CSI bus is also expected to appear in 2007 versions of
Intel’s x86 Xeon server CPUs, probably including the chip code-named Whitefield.

The CSI bus is optimized for low latency when used as a cache coherent
processor bus in four-processor systems. However, it can also be used to link up
to 16 CPUs for the high-end X86 systems built by OEMs such as IBM, NEC and
Unisys. In addition, CSI will be used without cache coherency as a standard way
to link north and south bridge chips in a processor core logic set. By using a
common interconnect as a chip-to-chip link, Intel will be able to develop
similar board-level designs and software tools for Itanium and Xeon systems.
That could reduce the costs of supporting the two server architectures.