243a Intel Haswell EP Platform Detailed

A certain DRAM major's frantic lobbying for the arrival of DDR4 seems to be paying off, as we're seeing some of the first leaks of information related to Intel's next-generation enterprise platform, Haswell-EP, slated for 2013-2014. Three crucial slides related to the platform component arrangement, the innards of the processor and core-logic themselves, were leaked. Haswell-EP will be built on the 22 nm silicon fabrication process, and will be perhaps the first platform to use DDR4 memory.

A certain DRAM major's frantic lobbying for the arrival of DDR4 seems to be paying off, as we're seeing some of the first leaks of information related to Intel's next-generation enterprise platform, Haswell-EP, slated for 2013-2014. Three crucial slides related to the platform component arrangement, the innards of the processor and core-logic themselves, were leaked.

The first and most important portion of a leaked slide reveals the arrangement of the various key components in the platform. It reveals an arrangement that is not much different from today's Sandy Bridge-EP platforms, in which n-number of CPU sockets are wired to each other using fast QuickPath Interconnect (QPI). Intel will use dual-channel QPI, which doubles bandwidth over what is available with today's enterprise platforms. Assuming each channel is clocked at 6.4 GT/s, the cumulative bandwidth would amount to 51.2 GB/s.

243b Intel Haswell EP Platform Detailed

Each socket will have four DDR4 DRAM channels. The DDR4 DRAM specification will introduce a fundamental change in the topology of DRAM components, which will be arranged "point-to-point". Each DRAM "channel" from the memory controller will support just one DRAM module, but there will be greater scope for DRAM makers to scale up densities of the modules with advancements in technology and silicon fabrication process. Much like Sandy Bridge-EP, Haswell-EP will see a bulk of the platform's PCI-Express lane budget being care of the processors' system agents; and will require external chipset for peripheral connectivity.

One significant and much-required change here is that the chipset will not hold the GbE interfaces for the platform. It is estimated that 1 GbE would reach obsoletion, at least in the enterprise space, in which faster interfaces such as 10 GbE, or even InfiniBand would have become "common". Since these are extremely bandwidth-hungry interfaces, Intel restructured the platform in a way that "common" onboard network interface controllers will be wired to the PCI-Express root complexes of the processors, rather than the chipset.

(this article is spread across three pages)