Intel Haswell-EP Platform Detailed

While the slides don't go into deep micro-architecture related details, it does give a fair idea of how things are arranged on the Haswell-EP die. The components on the chip are arranged much in the same way as they are, on Sandy Bridge-EP, only that the scale of things appear to have gone up. Oversimplified, the die consists of cores, their complementary slices of last-level cache (L3 cache), system agent, memory controller, PCI-Express root complex, and QPI root complex connected with a ring-bus. Components are enabled/disabled by controlling the "ring-stops" (points where the bus picks up or drops off data/instructions) for each of the components, to carve out the various SKUs based on the silicon.

243c Intel Haswell EP Platform Detailed

As mentioned earlier, 22 nm will be Intel's silicon fabrication process of choice, which will have matured quite a bit, when Haswell-EP's stint at the market arrives. While the diagram above doesn't give a clear picture about the number of cores Intel wants to cram onto the silicon, it's likely that there are 14 cores. One can deduce that looking at the total L3 cache amount mentioned (up to 35 MB), and amount of cache complementary to each core (around 2560 KB). That works out to 14 cores. Even in today's processor architectures by Intel, the L3 cache isn't a monolithic slab of SRAM, even though it is shared between all the cores. It consists of sub-divisions, which can be toggled to alter the amount L3 cache the various processor models end up with.

The system agent performs most of the ancillary functions of the processor. The integrated memory controller (IMC) will support the new DDR4 DRAM specification, which enables greater speeds and higher densities at lower voltages. The Haswell-EP IMC supports quad-channel DDR4-2133 MHz. The PCI-Express root complex will be PCI-Express Gen 3.0 compliant, and will include 40 lanes on the Haswell-EP and 24 lanes on Haswell-EN.

While every Haswell-EP processor comes with DMI, with which it can talk to the chipset, not every socket will be wired to the chipset. The sockets will be wired to each other in a kind of mesh-topology, using QPI links, and one of the processors will be wired to the chipset over DMI (and DMI-assisting PCI-Express links, if any).

A few other features mentioned in the above slide include HyperThreading, per core P-state, uncore frequency scaling, a newer version of Turbo Boost, and an integrated VRM control logic, which is probably how Intel will mandate a new VRD specification without bothering about inconsistencies between the various motherboards with regards to VRM design, out in the market.

The new processors will come with massive TDPs, in the range of 130~160 Watts.

Prev2 of 3Next
Use your ← → (arrow) keys to browse

While the slides don't go into deep micro-architecture related details, it does give a fair idea of how things are arranged on the Haswell-EP die. The components on the chip are arranged much in the same way as they are, on Sandy Bridge-EP, only that the scale of things appear to have gone up. Oversimplified, the die consists of cores, their complementary slices of last-level cache (L3 cache), system agent, memory controller, PCI-Express root complex, and QPI root complex connected with a ring-bus. Components are enabled/disabled by controlling the "ring-stops" (points where the bus picks up or drops off data/instructions) for each of the components, to carve out the various SKUs based on the silicon.

243c Intel Haswell EP Platform Detailed

As mentioned earlier, 22 nm will be Intel's silicon fabrication process of choice, which will have matured quite a bit, when Haswell-EP's stint at the market arrives. While the diagram above doesn't give a clear picture about the number of cores Intel wants to cram onto the silicon, it's likely that there are 14 cores. One can deduce that looking at the total L3 cache amount mentioned (up to 35 MB), and amount of cache complementary to each core (around 2560 KB). That works out to 14 cores. Even in today's processor architectures by Intel, the L3 cache isn't a monolithic slab of SRAM, even though it is shared between all the cores. It consists of sub-divisions, which can be toggled to alter the amount L3 cache the various processor models end up with.

The system agent performs most of the ancillary functions of the processor. The integrated memory controller (IMC) will support the new DDR4 DRAM specification, which enables greater speeds and higher densities at lower voltages. The Haswell-EP IMC supports quad-channel DDR4-2133 MHz. The PCI-Express root complex will be PCI-Express Gen 3.0 compliant, and will include 40 lanes on the Haswell-EP and 24 lanes on Haswell-EN.

While every Haswell-EP processor comes with DMI, with which it can talk to the chipset, not every socket will be wired to the chipset. The sockets will be wired to each other in a kind of mesh-topology, using QPI links, and one of the processors will be wired to the chipset over DMI (and DMI-assisting PCI-Express links, if any).

A few other features mentioned in the above slide include HyperThreading, per core P-state, uncore frequency scaling, a newer version of Turbo Boost, and an integrated VRM control logic, which is probably how Intel will mandate a new VRD specification without bothering about inconsistencies between the various motherboards with regards to VRM design, out in the market.

The new processors will come with massive TDPs, in the range of 130~160 Watts.

Prev2 of 3Next
Use your ← → (arrow) keys to browse
VR-Zone is a leading online technology news publication reporting on bleeding edge trends in PC and mobile gadgets, with in-depth reviews and commentaries.