The next major component in the Haswell-EP platform is its chipset, codenamed "Wellsburg." It will be branded Intel C610 series platform hub. Intel will take advantage of a newer silicon fabrication process (32 nm sounds likely), to cram more components on the chipset's silicon, without making it larger. To that effect, Intel mentioned the package size of the C610 doesn't exceed 25 x 25 mm, and its TDP (at maximum load) doesn't exceed 7W.
The chipset integrates a clock generator, it can share this clock with other components on the platform, or even be configured to rely on external clock signal. In terms of storage connectivity, we see a greater proliferation of new generation interfaces, such as SATA revision 3.0 and USB 3.0 SuperSpeed. The chipset can drive no less than ten SATA 6 Gb/s ports, with enterprise Rapid Storage Technology (RSTe) RAID support, with optional SSD caching (similar to Smart Response Technology). The C610 "Wellsburg" chipset will also feature a new USB port load-out, with six USB 3.0 and eight USB 2.0 ports. The reminiscent of today's GbE LAN PHYs are still there with the chipset, although it's unlikely that mainstram server boards will use it. Entry level ones will probably still use a couple of GbE controllers.
In conclusion, Haswell-EP looks like a monstrous concoction for enterprise platforms, with a focus on facilitating tomorrow's high bandwidth network interfaces.
The source of the slides is ChipHell.