Intel may drop the use of a high-k dielectric in the transistor gate stack at the 45nm manufacturing process node and is working on a second high-k material, with a yet higher dielectric constant (five times higher than that of silicon dioxide). The engineers were being encouraged to find a different engineering solution to the use of high-k. Intel’s high-k solution allows the 1.2-nm thick film of silicon dioxide gate insulation, used in Intel’s 90-nm and 65-nm process generations, to be replaced with 3.0-nanometers of the new material while achieving less than one hundredth of the gate leakage current. The use of high-k dielectrics would involve a minor additional complexity to the manufacturing process and thereby add a few percent to production costs, but that Intel was always looking for pragmatic ways to avoid or delay making such changes.

Intel may drop the use of a high-k dielectric in the transistor gate stack at the 45nm manufacturing process node and is working on a second high-k material, with a yet higher dielectric constant (five times higher than that of silicon dioxide). The engineers were being encouraged to find a different engineering solution to the use of high-k. Intel’s high-k solution allows the 1.2-nm thick film of silicon dioxide gate insulation, used in Intel’s 90-nm and 65-nm process generations, to be replaced with 3.0-nanometers of the new material while achieving less than one hundredth of the gate leakage current. The use of high-k dielectrics would involve a minor additional complexity to the manufacturing process and thereby add a few percent to production costs, but that Intel was always looking for pragmatic ways to avoid or delay making such changes.