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Intel Low Power 65nm Process In 2007

Intel is developing an ultra-low power derivative of its first-generation, 65-nm process technology. The technology, dubbed P1265, represents Intel’s first process that is tailored for ultra-low power chip applications, such as cellular phones, PDAs and other products. Slated to ramp up in the 2007 time frame, the P1265 process has demonstrated the ability to reduce transistor leakage by roughly 1,000 times over its current 65-nm technology for high-performance processors but transistor performance is lower by a factor of two. Intel has also manufactured a 50-megabit SRAM test chip based on the technology. The test chip is a 350-million transistor device with a cell size of 0.68-micron2. To enable P1265, Intel has modified its 65-nm process in three areas: the sub-threshold voltage, ultra-shallow junction and gate oxide.

Intel is developing an ultra-low power derivative of its first-generation, 65-nm process technology. The technology, dubbed P1265, represents Intel’s first process that is tailored for ultra-low power chip applications, such as cellular phones, PDAs and other products. Slated to ramp up in the 2007 time frame, the P1265 process has demonstrated the ability to reduce transistor leakage by roughly 1,000 times over its current 65-nm technology for high-performance processors but transistor performance is lower by a factor of two. Intel has also manufactured a 50-megabit SRAM test chip based on the technology. The test chip is a 350-million transistor device with a cell size of 0.68-micron2. To enable P1265, Intel has modified its 65-nm process in three areas: the sub-threshold voltage, ultra-shallow junction and gate oxide.

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