Here's an interesting thing we came across earlier today, Intel is considering getting a new PCI Express interface implemented, namely a two lane solution. Why? Well, simply because PCI Express x1 doesn't offer enough bandwidth for a lot of bandwidth hungry devices, but PCI Express x4 is too wide for many peripheral chips, especially considering Intel's chipset limitations.

Here's an interesting thing we came across earlier today, Intel is considering getting a new PCI Express interface implemented, namely a two lane solution. Why? Well, simply because PCI Express x1 doesn't offer enough bandwidth for a lot of bandwidth hungry devices, but PCI Express x4 is too wide for many peripheral chips, especially considering Intel's chipset limitations.

Many devices PCI Express peripheral chipsets such as SATA controllers and USB 3.0 host controllers really requires more than one lane of PCI Express bandwidth, as each lane in a PCI Express 2.0/2.1 system is "limited" to a theoretical maximum transfer speed of 5GT/s (Giga Transfers) or about 500MB/s, not taking into account overheads. PCI Express alleviates some of these problems by lowering the overhead and increasing the bandwidth per lane to 8GT/s or close to a real throughput of 1GB/s, but it's not that simple.

The problem is that Intel's upcoming Sugar Bay platform (Ivy Bridge + Panther Point) will only offer PCI Express 3.0 on the 16 lanes from the CPU, while the chipset will continue to offer eight lanes of PCI Express 2.0 bandwidth. In all fairness to Intel, the company has integrated USB 3.0 support in the chipset, but we're still only getting two SATA 6Gbps ports. Even so, the motherboard makers are going to want to slap on a few extra chips on their high-end boards, as has always been the case.

This doesn't quite solve the problem though, as even though we might see wider PCI Express lanes, the peripheral chip makers need to re-design their chips to support the extra bandwidth. Depending on the complexity and the design of the chip in question this might be a very simple task, or a very complex one. That said, for certain peripheral chips this is likely to make a lot of sense and we'd expect to see at least some implementations using this, well, that is if Intel actually goes ahead with its plan.

There's one other hurdle, the PCI-SIG which controls the PCI Express standard and as far as we're aware, there's currently no support for a x2 PCI Express interface. That doesn't meant that things couldn't change and it shouldn't be a very time consuming thing to do, as it's really just an addendum to the spec for a two lane interface. And if you were thinking that going x4 would make just as much sense, well, yes and no, as each PCI Express lane makes for a more complex IC and adding too many lanes would also increase the size of the chip. It's never as easy as you'd hope it would be, but hopefully Intel will also start to add more lanes to its future chipset and provide a wider bus between the CPU and chipset.