Intel Pentium 4 Prescott Review


prescott die Intel Pentium 4 Prescott Review
 

 
Northwood

Prescott
Die Size131mm2112mm2
Transistors55M125M
Gate length60nm50nm
Copper Interconnect67
ChemicalCobalt SilicideNickel Silicide
Lithography248nm193nm
SiliconNormal SiStrained Si
Trace Cache12µ-Ops12µ-Ops
L1 Cache8KB16KB
L2 Cache512KB1024KB
Pipelines20 stages31 stages
InstructionsFP, MMX, SSE, SSE2FP, MMX, SSE, SSE2, SSE3

At a glance, the Prescott die
measures at 112mm2 and contains 125 million CMOS transistors at 50nm
gate length. The transistors use features such as a 1.2-nm gate oxide thickness,
nickel silicide for low resistance. There are 7 layers of copper interconnects with a Low-k
dielectric material CDO that reduces crosstalk and power consumption and also
Strained Silicon technology to improve switching speed by making current flow
more smoothly. Prescott has

12Kµ-Ops of Trace Cache,
16KB of L1 cache and 1MB L2 cache 8-way set associative.

Diagram Intel Pentium 4 Prescott Review

Enhancements :

1. Enhanced NetBurst Architecture

A larger 16KB
L1 and 1MB Level 2 Cache allows the transfer of more data on each core clock,
delivering a much higher data throughput channel. This is especially important
in a HT Technology since two threads are running on one processor and
consequently need more cache space. Also Intel has several improvements to the
Branch Prediction Unit, Scheduler and Integer Execution core to offset for the
increase in pipelines

 

2. Longer Pipeline – 31 stages

Intel has confirmed that Prescott
has longer pipeline and the purpose of extending the pipeline is to boost clock
speed and doing less work per clock. However, a longer pipeline could mean more
stages to clear when there is a branch mis-prediction and that results in a loss
in performance. The number of stages in the pipeline of Prescott is stretched
to 31-stages so Intel must have a more efficient Branch Prediction Unit on
Prescott to reduce the misrate.

 

3. 90nm Process using Strained
Silicon Technology


strained silicon Intel Pentium 4 Prescott Review

Intel 90-nm process features low-power transistors of only 50-nm
in size. This new 90nm process on Prescott
combines higher-performance, lower-power transistors, strained silicon,
high-speed copper interconnects, and a new low-k dielectric material. Strained
silicon increases transistor drive current which improves switching speed by
making current flow more smoothly. Strained silicon is a process to raise drive
current in both types of CMOS transistors (NMOS and PMOS). Using a very thin
layer of single-crystal silicon with built in stress, or strain, improves drive
current, making the devices run faster. Intel’s strained silicon technology is
low cost, adding only about 2 percent to total wafer processing cost. Intel also
plans to use this strained silicon technique on the next-generation 65-nm
process technology and beyond.

 

4. 7 layers of
low-k copper interconnect with Low-K dielectric

Featuring a
new carbon-doped oxide dielectric material that reduces wire-to-wire
capacitance, enabling Intel to increase signal speed inside the chip and reduce
chip power consumption.
Reduced capacitance speeds up
intra-chip communication and reduces chip power. The process also integrates a
new carbon-doped oxide (CDO) dielectric material that increases signal speed
inside the chip and reduces chip power consumption. This dielectric is
implemented in a simple, two-layer stack design, which is easy to manufacture.

 

5. 13
New Instructions
(SSE3)

Designed to
improve performance for special application areas such as media and gaming.
These instructions are grouped into five areas: floating point to integer
conversions, complex arithmetic, video encoding, SIMD floating point using AOS
format and thread synchronization. Prescott’s New Instructions (PNI) include :

ADDSUBPD – Packed 64-bit add/subtract
ADDSUBPS – Packed 32-bit add/subtract
FISTTP – Store integer with truncation
HADDPD – Horizontal ADD 64-bit
HADDPS – Horizontal ADD 32-bit
HSUBPD – Horizontal SUBTRACT 64-bit
HSUBPS – Horizontal SUBTRACT 32-bit
LDDQU – Load unaligned 128-bit integer
MONITOR – Setup monitor addresses
MOVDDUP – Move 64-bit and duplicate
MOVSHDUP – Move 32-bit high and duplicate
MOVSLDUP – Move 32-bit low and duplicate
MWAIT – Monitor wait

FP to integer conversionsFISTTP
Complex arithmeticADDSUBPD, ADDSUBPS, MOVDDUP,
MOVSHDUP, MOVSLDUP
Video EncodingLDDQU
SIMD FP using AOS formatHADDPD, HSUBPD
HADDPS, HSUBPS
Thread SynchronizationMONITOR, MWAIT



MONITOR, MWAIT are thread synchronization instructions that will enhance HT but
the current Windows XP does not support them yet.

6. LaGrande security technology
(LT)

LaGrande Technology (LT) is a highly versatile set of hardware
enhancements added to Intel
CPU and Chipsets when used in conjunction with other platform components,
provides hardware based security support for the platform. Extensions to the
IA-32 architecture allow for the creation of multiple execution environments, or
partitions. This allows for the coexistence of a standard (legacy) partition and
a protected partition, where software can run in isolation in the protected
partition, free from being observed or compromised by other software running on
the platform. Access to hardware resources (such as memory) is hardened by
enhancements in the processor and chipset hardware. Other processor enhancements
include: event handling, to reduce the vulnerability of data exposed through
system events, instructions to manage the protected execution environment, and
instructions to establish a more secure software stack. LT
processing unit exist in Prescott will decrypt encrypted micro-code. In order
for LT to work, chipsets must be ready too, as such, the upcoming Intel 925X and
915 are expected to be LT ready. More on
LaGrande Technology.

 

7. 64-bit Extension – Yamhill (CT)

64-bit extension is touted to be
built into Prescott and Intel is expected to announce the CT officially in a few
weeks. Intel President and Chief Operating Officer Paul Otellini recently said
that Intel would likely give its 32-bit microprocessors an upgrade to 64 bits
once supporting software becomes available.

"You can be fairly confident that when there is software from an application
and operating system standpoint that we’ll be there," Otellini said, responding
to a question about 64-bit technology, in an interview with a Wall Street
analyst that was broadcast over the Web. Otellini said regular computer users
were unlikely today to spend thousands of dollars for computer memory for PCs
that can cost as low as $ 699. Eventually, however, as memory prices drop and
software becomes more complex, he said, breaking the 4-gigabyte memory limit
will make sense."

There is also an excellent article providing good deal of evidences about
Yamhill on Prescott here.
The article mentioned that the second 32-bit integer core is exclusively used
for 64 bit processing.

 

Prev2 of 14Next
Use your ← → (arrow) keys to browse


prescott die Intel Pentium 4 Prescott Review
 

 
Northwood

Prescott
Die Size131mm2112mm2
Transistors55M125M
Gate length60nm50nm
Copper Interconnect67
ChemicalCobalt SilicideNickel Silicide
Lithography248nm193nm
SiliconNormal SiStrained Si
Trace Cache12µ-Ops12µ-Ops
L1 Cache8KB16KB
L2 Cache512KB1024KB
Pipelines20 stages31 stages
InstructionsFP, MMX, SSE, SSE2FP, MMX, SSE, SSE2, SSE3

At a glance, the Prescott die
measures at 112mm2 and contains 125 million CMOS transistors at 50nm
gate length. The transistors use features such as a 1.2-nm gate oxide thickness,
nickel silicide for low resistance. There are 7 layers of copper interconnects with a Low-k
dielectric material CDO that reduces crosstalk and power consumption and also
Strained Silicon technology to improve switching speed by making current flow
more smoothly. Prescott has

12Kµ-Ops of Trace Cache,
16KB of L1 cache and 1MB L2 cache 8-way set associative.

Diagram Intel Pentium 4 Prescott Review

Enhancements :

1. Enhanced NetBurst Architecture

A larger 16KB
L1 and 1MB Level 2 Cache allows the transfer of more data on each core clock,
delivering a much higher data throughput channel. This is especially important
in a HT Technology since two threads are running on one processor and
consequently need more cache space. Also Intel has several improvements to the
Branch Prediction Unit, Scheduler and Integer Execution core to offset for the
increase in pipelines

 

2. Longer Pipeline – 31 stages

Intel has confirmed that Prescott
has longer pipeline and the purpose of extending the pipeline is to boost clock
speed and doing less work per clock. However, a longer pipeline could mean more
stages to clear when there is a branch mis-prediction and that results in a loss
in performance. The number of stages in the pipeline of Prescott is stretched
to 31-stages so Intel must have a more efficient Branch Prediction Unit on
Prescott to reduce the misrate.

 

3. 90nm Process using Strained
Silicon Technology


strained silicon Intel Pentium 4 Prescott Review

Intel 90-nm process features low-power transistors of only 50-nm
in size. This new 90nm process on Prescott
combines higher-performance, lower-power transistors, strained silicon,
high-speed copper interconnects, and a new low-k dielectric material. Strained
silicon increases transistor drive current which improves switching speed by
making current flow more smoothly. Strained silicon is a process to raise drive
current in both types of CMOS transistors (NMOS and PMOS). Using a very thin
layer of single-crystal silicon with built in stress, or strain, improves drive
current, making the devices run faster. Intel’s strained silicon technology is
low cost, adding only about 2 percent to total wafer processing cost. Intel also
plans to use this strained silicon technique on the next-generation 65-nm
process technology and beyond.

 

4. 7 layers of
low-k copper interconnect with Low-K dielectric

Featuring a
new carbon-doped oxide dielectric material that reduces wire-to-wire
capacitance, enabling Intel to increase signal speed inside the chip and reduce
chip power consumption.
Reduced capacitance speeds up
intra-chip communication and reduces chip power. The process also integrates a
new carbon-doped oxide (CDO) dielectric material that increases signal speed
inside the chip and reduces chip power consumption. This dielectric is
implemented in a simple, two-layer stack design, which is easy to manufacture.

 

5. 13
New Instructions
(SSE3)

Designed to
improve performance for special application areas such as media and gaming.
These instructions are grouped into five areas: floating point to integer
conversions, complex arithmetic, video encoding, SIMD floating point using AOS
format and thread synchronization. Prescott’s New Instructions (PNI) include :

ADDSUBPD – Packed 64-bit add/subtract
ADDSUBPS – Packed 32-bit add/subtract
FISTTP – Store integer with truncation
HADDPD – Horizontal ADD 64-bit
HADDPS – Horizontal ADD 32-bit
HSUBPD – Horizontal SUBTRACT 64-bit
HSUBPS – Horizontal SUBTRACT 32-bit
LDDQU – Load unaligned 128-bit integer
MONITOR – Setup monitor addresses
MOVDDUP – Move 64-bit and duplicate
MOVSHDUP – Move 32-bit high and duplicate
MOVSLDUP – Move 32-bit low and duplicate
MWAIT – Monitor wait

FP to integer conversionsFISTTP
Complex arithmeticADDSUBPD, ADDSUBPS, MOVDDUP,
MOVSHDUP, MOVSLDUP
Video EncodingLDDQU
SIMD FP using AOS formatHADDPD, HSUBPD
HADDPS, HSUBPS
Thread SynchronizationMONITOR, MWAIT



MONITOR, MWAIT are thread synchronization instructions that will enhance HT but
the current Windows XP does not support them yet.

6. LaGrande security technology
(LT)

LaGrande Technology (LT) is a highly versatile set of hardware
enhancements added to Intel
CPU and Chipsets when used in conjunction with other platform components,
provides hardware based security support for the platform. Extensions to the
IA-32 architecture allow for the creation of multiple execution environments, or
partitions. This allows for the coexistence of a standard (legacy) partition and
a protected partition, where software can run in isolation in the protected
partition, free from being observed or compromised by other software running on
the platform. Access to hardware resources (such as memory) is hardened by
enhancements in the processor and chipset hardware. Other processor enhancements
include: event handling, to reduce the vulnerability of data exposed through
system events, instructions to manage the protected execution environment, and
instructions to establish a more secure software stack. LT
processing unit exist in Prescott will decrypt encrypted micro-code. In order
for LT to work, chipsets must be ready too, as such, the upcoming Intel 925X and
915 are expected to be LT ready. More on
LaGrande Technology.

 

7. 64-bit Extension – Yamhill (CT)

64-bit extension is touted to be
built into Prescott and Intel is expected to announce the CT officially in a few
weeks. Intel President and Chief Operating Officer Paul Otellini recently said
that Intel would likely give its 32-bit microprocessors an upgrade to 64 bits
once supporting software becomes available.

"You can be fairly confident that when there is software from an application
and operating system standpoint that we’ll be there," Otellini said, responding
to a question about 64-bit technology, in an interview with a Wall Street
analyst that was broadcast over the Web. Otellini said regular computer users
were unlikely today to spend thousands of dollars for computer memory for PCs
that can cost as low as $ 699. Eventually, however, as memory prices drop and
software becomes more complex, he said, breaking the 4-gigabyte memory limit
will make sense."

There is also an excellent article providing good deal of evidences about
Yamhill on Prescott here.
The article mentioned that the second 32-bit integer core is exclusively used
for 64 bit processing.

 

Prev2 of 14Next
Use your ← → (arrow) keys to browse
VR-Zone is a leading online technology news publication reporting on bleeding edge trends in PC and mobile gadgets, with in-depth reviews and commentaries.