Intel hinted that the Front Side Bus (FSB) of their future processors could
go serial in 2007-8 timeframe. As Intel is gearing towards parallelism with
their multi-core CPU designs therefore the processor bus connecting the CPU and
chipset will be facing bandwidth bottleneck. This is the reason why the Dual
Core Xeon processor codenamed Dempsey will have two processor buses from the
CPUs to the chipset (Blackford & Greencreek) to overcome the bottleneck.

Another reason is that Intel is trying to increase the processor bus speed
which is also an important factor in CPU performance. However, the limitation of
the current parallel FSB will be felt when CPU FSB goes above 1.2Ghz. As we
know, Dual Core Smithfield will only feature 800Mhz FSB and even the 65nm
Allendale/Millville is to adopt 1066Mhz FSB therefore 1.2Ghz seems to be the
limitation for parallel FSB. Serial FSB must come about to overcome this
limitation.

According to the memory roadmap, DDR3 800/1066/1333 will be the memory
standard for processors in 2007-8 therefore memory interface will have to go
serial too. The memory interface will go serial in 2 stages; the first stage
implementation is done by using the Advanced Memory Buffer (AMB) chip for use in
FB-DIMMs to convert parallel bus into serial. Eventually it will reach a stage
where true Serial DIMM will come around.

Intel hinted that the Front Side Bus (FSB) of their future processors could
go serial in 2007-8 timeframe. As Intel is gearing towards parallelism with
their multi-core CPU designs therefore the processor bus connecting the CPU and
chipset will be facing bandwidth bottleneck. This is the reason why the Dual
Core Xeon processor codenamed Dempsey will have two processor buses from the
CPUs to the chipset (Blackford & Greencreek) to overcome the bottleneck.

Another reason is that Intel is trying to increase the processor bus speed
which is also an important factor in CPU performance. However, the limitation of
the current parallel FSB will be felt when CPU FSB goes above 1.2Ghz. As we
know, Dual Core Smithfield will only feature 800Mhz FSB and even the 65nm
Allendale/Millville is to adopt 1066Mhz FSB therefore 1.2Ghz seems to be the
limitation for parallel FSB. Serial FSB must come about to overcome this
limitation.

According to the memory roadmap, DDR3 800/1066/1333 will be the memory
standard for processors in 2007-8 therefore memory interface will have to go
serial too. The memory interface will go serial in 2 stages; the first stage
implementation is done by using the Advanced Memory Buffer (AMB) chip for use in
FB-DIMMs to convert parallel bus into serial. Eventually it will reach a stage
where true Serial DIMM will come around.