Intel will quietly signal what may be the company’s most
aggressive move to influence system memory architectures. In a paper entitled "A
2 Gb/s Point-to-Point Heterogeneous Voltage-Capable DRAM Interface", Intel
authors will disclose some details of a set of test chips that have validated an
Intel-designed high-speed DRAM interconnect scheme. By using 1.4V point-to-point
links, edge-rate control, selectable reference voltages and careful termination,
Intel measures data rates as high as 3.6 Gbits/s per pin, and argues that the
scheme is expandable to relatively wide banks of pins thus it could form the
backbone of large very fast DRAM main memory structures. In fact the scheme is
scalable enough to cover both quite small and very large arrays of DRAMs, and is
readily adaptable to existing DIMM modules and DRAM packages. Perhaps more
important, Intel has teamed with two DRAM vendors, Infineon and Samsung, to
demonstrate that the interface circuits can be built in existing DRAM processes
with no special provisions, and can operate in existing DDR2 packages.

Intel will quietly signal what may be the company’s most
aggressive move to influence system memory architectures. In a paper entitled "A
2 Gb/s Point-to-Point Heterogeneous Voltage-Capable DRAM Interface", Intel
authors will disclose some details of a set of test chips that have validated an
Intel-designed high-speed DRAM interconnect scheme.

By using 1.4V point-to-point links, edge-rate control,
selectable reference voltages and careful termination, Intel measures data rates
as high as 3.6 Gbits/s per pin, and argues that the scheme is expandable to
relatively wide banks of pins thus it could form the backbone of large very fast
DRAM main memory structures. In fact the scheme is scalable enough to cover both
quite small and very large arrays of DRAMs, and is readily adaptable to existing
DIMM modules and DRAM packages. Perhaps more important, Intel has teamed with
two DRAM vendors, Infineon and Samsung, to demonstrate that the interface
circuits can be built in existing DRAM processes with no special provisions, and
can operate in existing DDR2 packages.

Samsung will describe in detail their test chip, in which an
implementation of the Intel interface replaces the existing I/O strip on a
0.11-micron DRAM die with dummy memory arrays. Intel fabricated its own test
chip to simulate the behavior of a DRAM controller, and the companies
demonstrated 2 Gbit/s operation over an actual circuit board, and showed
convincing eye diagrams for simultaneous bidirectional operation.