Intel unveils more on ‘Knights Landing’
The latest Xeon Phi supercomputing chip from Intel has up to 3 teraflops of peak performance, and supports Intel’s new interconnect fabric known as Omni Scale.
At the International Supercomputing Conference in Leipzig, Germany on Monday Intel unveiled more details on its latest supercomputing chip called “Knights Landing.”
The high performance computing part got its first showing at the same event last year, but little was shared other than it would be manufactured using the 14 nanometer process node and would use integrated on-package memory. Intel revealed at this year’s show that the chip will use the Silvermont architecture, will be able to push out up to 3 teraflops of peak performance, and, most importantly, will use the Omni Scale interconnect fabric.
Not much is known about the technical details Omni Scale yet, but Intel said it would be a scalable future-proof platform that would support everything from PCIe adapters, edge switches, director systems, to Intel’s own silicon photonics and open software tools. With it, Intel says, the bandwidth bottleneck will be a thing of the past.
“One of the choke points in many applications used today is I/O and memory bandwidth, and this is specifically designed to remove that bottleneck,” Charles Wuischpard, Intel’s boss of the Workstations and HPC division, is quoted as saying.
For memory the chip will pack 16GB of stacked memory based on Micron’s Hybrid Memory Cube technology, which uses Through Silicon Via (TSV) technology. This is said to provide five-times the bandwidth of off-chip DDR4.
The number of cores on the chip has not yet been revealed, but 72 has been floated around as a possible number.
Knights Landing is expected to start shipping to commercial HPC systems in the second half of 2015.