Intel Xeon MP “Cranford” B-0 Stepping

Boxed Intel Xeon Processor MP will undergo the following changes for the A-0
to B-0 core processor stepping change :
CPUID will change from F41 to F49
B-0 is pin compatible with A-0
New S-Specs for converting products
B-0 stepping will also be the conversion to a Pb-free second level
interconnect (SLI) / RoHS Compliant with Flip Chip Exemption

 Intel Xeon MP Cranford B 0 Stepping

Boxed Intel Xeon Processor MP will undergo the following changes for the A-0
to B-0 core processor stepping change :

  • CPUID will change from F41 to F49
  • B-0 is pin compatible with A-0
  • New S-Specs for converting products
  • B-0 stepping will also be the conversion to a Pb-free second level
    interconnect (SLI) / RoHS Compliant with Flip Chip Exemption

The following will be fixed in a B-0 stepping

  • J64. A#[39:37] Always Have ODT (On Die Termination) Enabled
    Problem : ODT will be enabled on the end agents and middle agents for signals
    A#[39:36], resulting in a VOL increasee, which may create system level timing
    problems
  • Implications : Signal quality analysus shoudl be review for these signals.
    Systems which do not use signals A#[39:36 (typically with <64GB of
    addressable memory) are not exposed to this issue
    This issue (A#[39:36] always have ODT enabled) has been fixed on B-0 stepping.
    ODT on the end agents and middle agents for signals A#[39:36] now meets
    specifications as described in the datasheet.
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