As it became common recently, Intel is unveiling the high end members of each new microarchitecture, or optical shrink, nearly a year after showing it in mainstream part. The same is expected to happen with Ivy Bridge – what does Intel have in store for top end users?
As you all know by now, in about two weeks Intel will be unveiling its first Ivy Bridge 22 nm processors, the new semiconductor process shrink of the Sandy Bridge architecture with lower power and a couple of improvements like better integrated graphics and random number generators, for instance, thrown in. The initial parts will be mainstream desktop then mobile, with the much expected UltraBook range later in early summer.
What about the high end desktop as well as the widely popular dual socket servers and workstations, not to forget the top end quad socket machines? Well, we are likely to wait at least till year-end for Ivy Bridge update to those platforms. And, guess what, there are two major differences there.
The dual processor Socket 2011 platform, the Xeon E5, is expected to receive the ten core 25 MB L3 (some sources mention 30 MB L3 but that doesn't seem likely as of now) cache Ivy Bridge EP part update, which should also bring around 15%-20% clock speed update. The 22 nm tri-gate process benefits for both power consumption and clock speed will help Xeon E5 solve the high-TDP problems that bothered it a little bit in the Sandy Bridge EP generation right now. In my mind, based on the power and performance gains assessment, I'd expect 2.4 GHz 10-core parts at the 95W TDP level, 3 GHz 10-core parts at the 130W TDP level, and 3.3 GHz 10-core parts at the 150W workstation SKU grade, all plus minus 100 MHz or so.
And, oh yes, the TDP problem solution should also enable the single Socket 2011 systems based on X79 chipset to have full speed 8-core and 10-core chips in this iteration – good news for those of you holding, say, entry level Core i7-3820 quad core, since this would make a nice speed doubling upgrade without increasing the system power consumption.
Again, this will be just a CPU update on the same chipset and board platform, likely to be matched with a Patsburg C600 chipset stepping update for those 'minor problems' like say 6 Gbps SAS, for instance. Otherwise, the stable platform should provide a smooth transition from 8-core Sandy Bridge EP to 10-core Ivy Bridge EP.
Around that timeframe, the quad socket and above Ivy Bridge EX 'Xeon E7' should appear as well. Hold on, we did look at Westmere EX before, but what happened to the Sandy Bridge EX? Well, nothing – it will never exist in the market. Simply, the large multi-core dies required for big servers take their toll on what can be put inside, both feature and clock speed-wise. To move substantially forward from the 10-core Xeon E7 4870 Westmere EX, and keep the TDP under check, we needed the use of 22 nm process, that's why Sandy Bridge EX was skipped, and Intel moved right onto Ivy Bridge EX.
Now, this should also bring the EX family closer to EP in terms of launching closer to each other, with less delays suffered by the big brothers. The thing is, Ivy Bridge EX will be a new platform, but quite similar to the Ivy Bridge EP. The same Patsburg I/O chipset will be used as well as the same DDR3-1600 server memory (although Ivy Bridge EP should also support DDR3-1866).
Now, the differences start here: the quad socket Ivy Bridge EX is expected to have 15 – hopefully they can round it up to 16 for binary system sake – cores, with similar per-core cache size as the Ivy Bridge EP, but correspondingly slower core speed: I don't think they'll go much above 2.4 GHz, the same clock speed as Westmere EX Xeon E7 4870 top model. The four memory controllers using new version of scalable memory buffer chip effectively support eight DDR3-1600 memory channels and 1.5 TB memory per socket, and there are more QPI channels as well – three compared to two on the EP platform, but less than four in the Westmere EX platform.
Since there are 32 PCIe 3.0 lanes on each CPU here (strangely, less than 40 lanes per socket on the EP but then, there are more sockets here), we can be excused for needing less QPI links there, but then, three links only allow four CPUs to be connected directly without hops, and even adding accelerators like MIC on the QPI would then create extra hops in the system, which do add latency. Since the same platform is to be shared by the future Haswell EX and Broadwell EX as well, it'd be a pity of the QPI link number limitation becomes a real bottleneck later, once more QPI co-processors or I/O controllers are out there.
In summary, Intel will round up its Ivy Bridge platform rollout within about a year, with dual socket Xeon E5 and quad processor Xeon E7 platform updates,which will share common I/O chips, QPI speeds and even server memory speeds, yet with record numbers of high-end cores per chip as well as some very interesting performance records along the way.