Techreport
has learned that a chip-level problem has impacted the supply of
these chips to both server OEMs and distribution channel customers. It is
related to the translation lookaside buffer (TLB) in the processor’s L3 cache.
The erratum can cause a system hang with certain software workloads. The erratum
is present in all AMD quad-core processors up to the current B2 revision. A
revision B3 is in the works and expected in Q1. This bug too affects the newly
introduced Phenom 9500 and 9600 processors. Although AMD has a fix for the
problem in the works now but it degrades performance by 10%. Future revisions of
the Phenom, including the planned Phenom 9700 model at 2.4GHz and the 9900 at
2.6GHz, will include the fix. AMD plans to replace the current Phenom 9500 and
9600 models with new 9550 and 9650 models, based on the B3 chip and more than
two triple-core Phenom variants by the end of Q1.


Techreport
has learned that a chip-level problem has impacted the supply of
these chips to both server OEMs and distribution channel customers. It is
related to the translation lookaside buffer (TLB) in the processor’s L3 cache.
The erratum can cause a system hang with certain software workloads. The erratum
is present in all AMD quad-core processors up to the current B2 revision. A
revision B3 is in the works and expected in Q1. This bug too affects the newly
introduced Phenom 9500 and 9600 processors. Although AMD has a fix for the
problem in the works now but it degrades performance by 10%. Future revisions of
the Phenom, including the planned Phenom 9700 model at 2.4GHz and the 9900 at
2.6GHz, will include the fix. AMD plans to replace the current Phenom 9500 and
9600 models with new 9550 and 9650 models, based on the B3 chip and more than
two triple-core Phenom variants by the end of Q1.