During the keynote speech at the Mentor Graphics User Conference, Sameer Halepete, Vice President of VLSI Engineering at NVIDIA Corporation, said that the industry has to move to 450mm wafers as soon as possible.
Recently, NVIDIA presented at the Mentor Graphics User Conference and openly discussed the difficulties semiconductor industry faces. No one, not even Intel can no longer deny that building semiconductors is reaching new heights in complexity. After all, we all know how the 22nm roadmap looked before and the reality where actual products are arriving only next week.
In the view of Sameer Halapete, VP of VLSI Engineering at NVIDIA Corporation, there are numerous challenges for the semiconductor industry as a whole, from process node, UltraViolet vs. Extreme UV lithography, bulk silicon versus Fully-Depleted SOI – which is contemplated by Intel as the first SOI to be used by the company for its optical chips. The innovation can no longer come from the die shrink itself, but rather through increasing the amount of chips that is being processed on a single wafer.
Naturally, the solution is a move from 300mm wafers of today into 450mm wafers of tomorrow. The difference how many chips can be manufactured using a larger wafer is quite amazing, just as amazing was the change from 200mm wafers onto 300mm back at the beginning of 21st century with Intel Pentium 4 being the first mass produced part. 200mm to 300mm conversion lead to price reduction of 30-40% in chip cost, while the 300mm to 450mm cost saving is being estimated at 40-55%.
Truth to be told, NVIDIA does not expect to see 450mm wafer manufacturing arriving in time for the 14nm process node, which is scheduled to arrive after 28nm and 20nm. Depending on a manufacturer, 14nm is scheduled for 2014/15.
According to a story on EETimes, the reasons why NVIDIA wants to push for 450mm wafers are identical to ones from Qualcomm. The world's largest foundry (TSMC) recently changed its business model and eroded the relationships with companies such as NVIDIA. By starting to charge for each wafer rather than for each working die raises the costs for every fabless semiconductor, regardless of size or target market.
This goes hand in hand with the continuous evaluation of other foundries. For example, in the semiconductor industry, it was always widely known that a certain NVIDIA openly executive said to Doug Grose, former CEO of GlobalFoundries. NVIDIA would refuse to commit to GlobalFoundries for as long as AMD has a single share in the company. Given that AMD recently traded all of its shares back to GlobalFoundries, there are no limitations why NVIDIA would not join AMD, IBM and Qualcomm in manufacturing its silicon in one of many foundries GlobalFoundries operates.
Furthermore, NVIDIA recently received test chips from Samsung Semiconductor, allegedly from the Austin facility which delivers chips to Apple and naturally, Samsung themselves. Even though Samsung is competing with NVIDIA Tegra with its Exynos chips, the name of the game is to have as much customers to share the cost and risk as possible, rather than Us vs. Them mentality which exists only on lower levels.
For example, NVIDIA recently introduced Kepler GPU architecture, powering the GeForce GTX 680. The die size of the GK104 chip is just 294mm2, packing 3.5 billion transistors. Should the industry switch from 300mm to 450mm wafer size, NVIDIA could cram about 540 GK104 chips. On 300mm wafer, NVIDIA can only fit about 240 chips – more than twice as much chips per single wafer! Now, if that was a 294mm2 die, which is fairly large – imagine how many Tegra chips can fit on a single 300mm wafer. For the record, T30 die size is counted at 82mm2, while T20 (Tegra 2) was 49mm2.
This problem will only get more complex, especially after the company unveils the seven billion transistor Kepler GPU at the GPU Technology Conference – which will take place from May 14-17 in San Jose, California.