PCI Express 2.0 Specs

PCI-SIG has made the release candidate (revision 0.9) of its PCI Express Base 2.0 specification available for review by member companies. With work on this specification nearly complete, PCI-SIG assigned its technical workgroups to investigate and develop the scope for potential extensions of the PCI Express protocols to meet future requirements, such as improved dynamic power controls, optimized synchronization, coherency hints, and more efficient transaction ordering. This specification extends the data rate of PCIe to 5GT/s in a manner compatible with the existing PCIe 1.1 specifications that support 2.5GT/s signaling.

PCI-SIG®, the Special Interest Group responsible for the ubiquitous PCI
Express® industry-standard I/O architecture, announced today that it has made
the release candidate (revision 0.9) of its PCI Express Base 2.0 specification
available for review by member companies. With work on this specification nearly
complete, PCI-SIG assigned its technical workgroups to investigate and develop
the scope for potential extensions of the PCI Express protocols to meet future
requirements, such as improved dynamic power controls, optimized
synchronization, coherency hints, and more efficient transaction ordering.

These enhancements will be evaluated for possible inclusion in a collection of
incremental extensions to the PCI Express architecture intended to improve the
range of design options available to emerging markets and computing models. The
affected technical workgroups have issued a call for new membership and will
study future extensions such as, but not limited to, those within the recent
Geneseo proposal from PCI-SIG member companies. These technical workgroups,
which are open to all members of the organization, will solicit input from other
member companies and recommend future directions to enhance the PCI Express
protocols.

PCIe 2.0 Specifications

PCI-SIG has released the 0.9 version of the PCIe Base 2.0 specification for
member review and comment. This specification extends the data rate of PCIe to
5GT/s in a manner compatible with the existing PCIe 1.1 specifications that
support 2.5GT/s signaling. There are a number of improvements made to the
protocol and software layers of the architecture—a product of more than three
years of design experience by the PCI-SIG members. A companion Card
Electromechanical (CEM) 2.0 specification is also currently in review at 0.5 by
the PCI-SIG members.

“PCI-SIG is pleased with the impressive progress in the proliferation of the PCI
Express technology by our members,” said Al Yanes, PCI-SIG chairman. “We are
committed to providing a compelling technology roadmap for our flagship PCI
Express architecture. With the release of PCIe Base 2.0 for member review, we
look forward to new protocol improvements, and IOV and PCIe Cable
specifications.”

I/O Virtualization and PCIe Cable Specifications

Continuing ongoing specification development, PCI-SIG working groups are
completing the suite of specifications to enable I/O device virtualization and
sharing. The draft Address Translation Services (ATS) 0.9 specification has been
released for member review. The Single-Root and Multi-Root device sharing
specifications are in various stages of development and will be released to
members for review in the near future.

The PCIe Cable specification has been released to members at revision 0.9 for
60-day review. The new specification supports cables up to 10 meters in length
running at 2.5 Gb/s. Cable assemblies have already been measured and validated
by the workgroups. The specification will primarily be implemented in
disaggregated I/O and backplane usage models. PCI-SIG has decoupled this
specification from the PCIe 2.0 specification (5.0 GT/s) and anticipates the
final version of the cable specification to be ready by year-end 2006.

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