Samsung announced three next-generation memory devices: a 4Gbit NAND flash chip made on 70nm processing, a 3Gbs data rate DRAM using a 3D transistor design, and a monolithic 512Mb NAND flash and logic interface on the same chip.

Samsung had developed a 3D transistor, which it calls Recess Channel Array Transistor (RCAT), for a 512Mb DRAM. The 3D transistor reduces the memory cell size, resulting in a much higher density. The new DRAM is made on 80nm process node. The device operates at less than 1.5V, which is the proposed voltage for the projected DDR3 DRAMs.