Samsung is the first manufacturer in the industry to begin mass producing DDR2 DRAM – 512 Megabit (Mb) – on an 80 nanometer (nm) scale. With 80-nm process technology, Samsung is able to increase its production efficiency by 50 percent over the previous 90-nm process. The production economies of scale afforded by moving to 80-nm process technology will better enable the company to meet increasing demand for DDR2. The move to 80-nm circuitry was sped up by the use of a recess channel array transistor (RCAT). This three-dimensional transistor layout greatly enhances the refresh rate, which is a critical element in data storage. Samsung’s RCAT also reduces cell area coverage, which allows for increased process scaling by freeing up space for chip-per-wafer growth

Samsung Electronics Co., Ltd., the world leader in advanced memory
technology, announced today that it is the first manufacturer in the industry to
begin mass producing DDR2 DRAM – 512 Megabit (Mb) – on an 80 nanometer (nm)
scale.

With 80-nm process technology, Samsung is able to increase its production
efficiency by 50 percent over the previous 90-nm process. The production
economies of scale afforded by moving to 80-nm process technology will better
enable the company to meet increasing demand for DDR2.

"With demand for DDR2 at its highest level since its market debut in 2004, our
80-nm technology provides us with the ability to more efficiently support the
sustained demand growth that is expected in the DDR2 marketplace this year,"
said Tom Trill, director, DRAM Marketing, Samsung Semiconductor, Inc.

Samsung was able to smoothly transition from 90-nm to 80-nm process technology
because it utilized many of the basic features of 90-nm geometries, and as a
result required minimal upgrades to its fabrication lines.

The move to 80-nm circuitry was sped up by the use of a recess channel array
transistor (RCAT). This three-dimensional transistor layout greatly enhances the
refresh rate, which is a critical element in data storage. Samsung’s RCAT also
reduces cell area coverage, which allows for increased process scaling by
freeing up space for chip-per-wafer growth.