The long awaited Xeon E5 family, where the full potential of Socket 2011 is realised, is now expected only some weeks after the Chinese New Year. Creating a feature-loaded 8-core die aimed at a very wide range of performance and power options was a challenge, even in Intel's highly tuned 32 nm process. As their desktop brethren are being unveiled this week, here we update you with the situation on the dual socket front.
When the first specs rumours of Socket 2011 CPUs appeared well over a year ago, they left everyone in the industry in awe: here you had THE ULTIMATE 32 nm process CPU. A total of 8 capable Sandy Bridge generation cores, coupled with a generous 20 MB cache are fed by four channels of DDR3 memory and two QPI channels completely free for inter-CPU communication – since 40 PCIe v3 lanes plus DMI2 directly attached on-chip take care of the general purpose I/O. Wow!
Now, you may say, so what – Westmere-EX Xeon E7 parts pack 10 cores and 30 MB cache, 4 memory and 4 QPI links together in that same process for over half a year now in shipping systems. However, that CPU design is tuned for specific power and frequency band, and one specific usage in MP servers, full stop. On the other hand, the E5 design has to cover everything from low-power blades to 4-socket servers to ultrafast workstations with TDP of more than 150W per socket and, yes, their high-end desktop brethren under the Core i7 moniker. And, Sandy Bridge core takes a little bit more logic space than the Westmere one.
Anyway, Intel also didn't have that much competitive pressure in the X86 space to really feel rush to get the new generation out of the door till now, however the product is done and needs to be brought to the market. So, what's the situation right now, and what Intel could do further to improve the vast potential that Socket 2011 brings along? Let's see what the sources say:
First, Intel did have issues with both the CPU and the Patsburg chipset, the virtualisation engine and SAS port ones being the most widely publicised around the Net. With the C-2 CPU stepping to be out around year end, and the 'good enough' chipset version out there, the mid-February rollout looks on schedule now.
The greater issue to solve is the device's power. Yes, all these cores and caches and I/O channels of all kinds do demand a lot of juice, leading to one of the reasons why only 6 out of 8 cores are enabled on the desktop version, for instance. On the high end proper Xeon E5, the high end workstation version might start at only reach just above 3 GHz, even with a very generous 150W TDP headroom, when using all 8 cores and 20 MB L3 cache. Within the standard 95W TDP bracket, most of these CPU are not expected to run above 2.5 GHz in the initial round, compared to nearly 3 GHz for the Westmere ones.
Of course, each of the new cores is faster per-clock than the older ones, and the memory & I/O improvements more than make up for the clock speed loss. But, frequency still matters, and there will be expectations of improvements here soon.
Enter the D-stepping sometime in Q2 next year, the one that always brings the good news on the performance front – remember both Nehalem and Westmere in the recent past. Now, if the combination of device and process tune ups for that stepping gives us, say, an extra 10% power-performance gains, we could see a few good things emerging. First, the high end workstation part would, likely at 3.3 GHz, finally match the clock frequency of its Westmere predecessor while providing a third more core count, while the same would then also apply to the desktop, finally enabling a true 8-core Core i7, very likely priced at a huge premium.
Second, the generic bread-and-butter 95W server parts would come closer to the 2.8 GHz or so, becoming more attractive as a Nehalem replacement of the similar clocked 4-core processor platforms from 3 years ago. The frequency does matter in marketspeak here, as it is much easier to do a sale then, rather than trying to replace 2.93 GHz processors with 2.5 GHz ones, no matter how much better.
So, the D-stepping of the CPU, together with the final revision of Patsburg chipset and, hopefully, the resolve of the PCIe v3 compatibility doubts, would mark the maturing of the ultimate 2011 high end X86 workstation and server platform. Next then would come the Ivy Bridge-EP generation of the Xeon E5, likely a year later in early 2013 – although, personally, I would like to see them at the end of 2012 rather.
According to our sources, Ivy Bridge-EP generation will basically cram more cores, 10 of them, and 25 MB of L3 cache, keeping the same 2.5 MB L3 per core proportion, yet likely faster DDR3 memory speeds too, beyond DDR3-1866. Now, knowing the target markets and certain taper-offs of performance returns, I would have hoped for an 8-core die with 32 MB L3 cache instead, offering better cache hit rates for the demanding AVX vector codes and computing apps. Now, of course, the balance has to be struck, and Intel has many markets to address with this die too. One thing is certain – if the 22 nm tri-gate process brings on its promises, you will likely have a powerful 10-core desktop and workstation parts running at well, well above 3 GHz, all in the same Socket 2011 as what the upcoming Core i7 and Xeon E5 processors bring over this and next quarter.