SimpleTech & AMD Devise DDR3 For AM3 K8L

SimpleTech today announced the joint effort between SimpleTech and AMD to define registers and modules for a DDR3 SDRAM RDIMM. DDR3 RDIMM modules are planned as the natural evolution over today’s DDR2-based solutions and designed to deliver the increased performance and energy efficiency required for future commercial servers and workstations. The work of the two companies is being conducted within JEDEC, a coalition of approximately 270 companies focused on the creation of open standards for the solid-state technology industry. Densities are designed to range from 512MB to 32GB. Initialization scheme, parity function as well as control registers were approved by JEDEC in March. Validation is under way, testing is expected to begin in 2007 and full production is planned by 2008.

SimpleTech, Inc. (Nasdaq:STEC) today announced the joint effort between
SimpleTech and AMD (NYSE:AMD) to define registers and modules for a DDR3 SDRAM
Registered Dual-Inline Memory Module (RDIMM).

DDR3 RDIMM modules are planned as the natural evolution over today’s DDR2-based
solutions and designed to deliver the increased performance and energy
efficiency required for future commercial servers and workstations. The work of
the two companies is being conducted within JEDEC, a coalition of approximately
270 companies focused on the creation of open standards for the solid-state
technology industry.

"AMD’s collaboration on the development of the DDR3 RDIMM architecture and
design was essential to a successful solution," said Bill Gervasi, vice
president of DRAM technology at SimpleTech. "AMD’s input during the definition
phase and participation in developing the RDIMM and defining the SPD
configuration EEPROM drove progress forward," he added.

"AMD and SimpleTech are leading an open and collaborative effort within our
industry to drive DDR3 along a seamless upgrade path, combined with a step
function improvement in performance-per-watt characteristics," said Levi Murray,
director of technology enabling and infrastructure development at AMD. "By
working collectively as a member of JEDEC, we can better ensure the benefits of
this technology are fully achieved with minimal disruption, maximum investment
protection and improved economic opportunities for the entire value chain."

The two companies had specific roles in defining the overall solution. AMD
defined the timing of the interface and termination characteristics while
SimpleTech defined the register component to support standard height as well as
VLP and ATCA applications. In this new design, register and PLL functions are
integrated into a single device to reduce overall system power consumption.

In addition to including control words that permit device configuration and
allow vendors to add new functions over time, SimpleTech also initiated the
inside-out dual fly-by signaling approach used for all DDR3 RDIMM layouts.

Densities are designed to range from 512MB to 32GB. Initialization scheme,
parity function as well as control registers were approved by JEDEC in March.
Validation is under way, testing is expected to begin in 2007 and full
production is planned by 2008. For more information, please visit:

www.simpletech.com/oem/ddr3rdimm.php

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