Sony, IBM and Toshiba announced that they would reveal technical details of CELL, a microprocessor that the companies have been jointly developing for next-generation entertainment applications. The companies are preparing five technical papers for the forum. In particular, the focus is likely to be placed on “The Design and Implementation of a First-Generation CELL Processor” (session code 10.2), in which the developers will disclose the key concepts of CELL. The chip to be exhibited integrates a CPU core based on the Power architecture and several signal processors for streaming data processing, using 90nm SOI process technology. The companies are planning two other papers on the signal processors: “A Streaming Processing Unit for a CELL Processor” (session code 7.4) and “A 4.8GHz Fully Pipelined Embedded SRAM in the Streaming Processor of a CELL Processor” (session code 26.7).

Sony, IBM and Toshiba announced that they would reveal technical details of
CELL, a microprocessor that the companies have been jointly developing for
next-generation entertainment applications, at the International Solid-State
Circuits Conference (ISSCC 2005) to be held in the US from February 6 to 10,
2005. The companies are preparing five technical papers for the forum. In
particular, the focus is likely to be placed on "The Design and Implementation
of a First-Generation CELL Processor" (session code 10.2), in which the
developers will disclose the key concepts of CELL.

The chip to be exhibited integrates a CPU core based on the Power
architecture and several signal processors for streaming data processing, using
90nm SOI process technology. The companies are planning two other papers on the
signal processors: "A Streaming Processing Unit for a CELL Processor" (session
code 7.4) and "A 4.8GHz Fully Pipelined Embedded SRAM in the Streaming Processor
of a CELL Processor" (session code 26.7). Other papers related to the CELL
processor on schedule include "A Double-Precision Multiplier with Fine-Grained
Clock-Gating Support for a First-Generation CELL Processor" (session code 20.3)
by IBM, and "Clocking and Circuit Design for a Parallel I/O on a
First-Generation CELL Processor" (session code 28.9) by Rambus Inc and Stanford
University of the US.