products processors Tilera 64 Cores CPU 10X Faster, 30X Cooler than Dual Core Xeon

Tilera today launched the TILE64™ processor, the first in a
family of Tile Processor™ chips based on a revolutionary architecture that can
scale to hundreds and even thousands of cores. The TILE64 processor contains 64
full-featured, programmable cores – each capable of running Linux – and delivers
10X the performance and 30X the performance-per-watt of the Intel dual-core
Xeon, and 40X the performance of the leading Texas Instruments DSP*. Initial
target markets for the TILE64 processor include the embedded networking and
digital multimedia markets. Production pricing for the TILE64 family
starts at $ 435 in 10K unit quantities. Tilera’s roadmap also includes plans for
a 36-core and a 120-core device.

products processors Tilera 64 Cores CPU 10X Faster, 30X Cooler than Dual Core Xeon

Tilera Corporation today launched the TILE64™ processor, the first in a
family of Tile Processor™ chips based on a revolutionary architecture that can
scale to hundreds and even thousands of cores. The TILE64 processor contains 64
full-featured, programmable cores – each capable of running Linux – and delivers
10X the performance and 30X the performance-per-watt of the Intel dual-core
Xeon, and 40X the performance of the leading Texas Instruments DSP*. Initial
target markets for the TILE64 processor include the embedded networking and
digital multimedia markets.

Tilera was founded in 2004 to bring to market the MIT research of Dr. Anant
Agarwal who first created the mesh-based multicore architecture in 1996. The
"Raw" project received multi-million dollar DARPA and National Science
Foundation grants and spawned the development of the first tiled multicore
processor prototype and associated multicore software in 2002. Backed by this
immense body of work, Tilera holds 40-plus patents pending and a significant
lead over other processor and DSP companies who are only now recognizing a need
to adopt a similar multicore approach. Tilera has a dozen customers who are
currently integrating the TILE64 processor into products in the advanced
networking and digital multimedia space.

"This is the first significant new chip architectural development in a decade,"
said Tilera President and C.E.O., Devesh Garg. "We developed this new
architecture because existing multicore technologies simply cannot scale beyond
a handful of cores. Moreover, customers have repeatedly indicated that the
current multicore software tools are very primitive because they are based on
single-processor-core models. We’re introducing a revolutionary hardware and
software platform that has solved the fundamental challenges associated with
multicore scalability."

diagram tile64 Tilera 64 Cores CPU 10X Faster, 30X Cooler than Dual Core Xeon

Tilera’s iMesh™ Interconnect
Tilera’s new architecture provides superior performance because it eliminates
the on-chip bus interconnect, a kind of centralized intersection that
information must flow through between cores within the chip, or before it leaves
the chip. As engineers have added more cores to chips, the bus has created an
information traffic jam because packets from these cores all must travel to one
central point, like a spoke-and-wheel traffic intersection in an old city.

Tilera’s technology eliminates the bus by placing a communications switch on
each processor core and arranging them in a grid fashion on the chip. This
creates an efficient 2-dimensional traffic system for packets, much like the
layout of a modern city’s streets. Tilera’s implementation of this grid
architecture is called iMesh (intelligent Mesh), and it incorporates a number of
patented innovations that enhance the performance and flexibility of the mesh.
Because the aggregate bandwidth is orders of magnitude greater than a bus and
the distance between cores is shorter, the iMesh technology can be leveraged to
create grids as large or small as an application requires, creating a
"computing-by-the-yard" scalability, with breakthrough performance and ultra-low
power consumption.

The TILE64 Processor Specifications
Each of the 64 cores on the TILE64 processor is capable of running its own
operating system, such as Linux, and provides dramatically more compute
performance than any other competing multicore device. Each core is a
full-featured, general-purpose processor that includes L1 and L2 caches, as well
as an innovative distributed L3 cache. The cores are overlaid with the iMesh
network, which provides extremely low-latency, high bandwidth communications
between the cores, memory and the I/O.

In order to minimize total system power, cost and real estate, the TILE64
processor integrates four DDR2 memory controllers and a complete array of high
speed I/O interfaces, including two 10 Gbps XAUI, two 10 Gbps PCIe, two 1 Gbps
Ethernet RGMII, and a programmable flexible I/O interface to support interfaces
such as compact flash and disk drives.

The TILE64 processor is ideally suited for high performance embedded system
markets. In the networking and telecommunications areas, the TILE64 processor is
designed into switches and security appliances to provide unmatched performance
of up to 20 Gbps of L4-L7 services. In the digital video and multimedia market,
the TILE64 delivers an unprecedented two streams of broadcast-quality,
high-definition H.264-encode capability in a single chip, and more than ten
streams of encode for high-definition video conferencing applications.

The Multicore Development Environment™ (MDE)
The TILE64 processor is supported by the most robust set of software tools ever
designed for multicore processor technology. The toolset is based on an
industry-proven, open programming environment and adds advanced multicore
debugging and profiling techniques to accelerate developer productivity and time
to market.

The Tilera MDE includes a powerful Eclipse-based Integrated Development
Environment (IDE), an ANSI standard C compiler, a full-system simulation model
and a set of flexible command-line interfaces. The MDE also provides innovative,
graphically-driven tools for debugging and profiling multicore processors, and
an application level library that provides lightweight socket-like stream
communication mechanisms. The TILE64 processor supports this immense body of
open source tools and applications with the standard SMP Linux programming
environment.

Pricing and Availability
The TILE64 processor is available now in three different device variants based
on frequency and I/O capabilities. Production pricing for the TILE64 family
starts at $ 435 in 10K unit quantities. Tilera’s roadmap also includes plans for
a 36-core and a 120-core device. More information on Tilera and the TILE64
processor can be found on Tilera’s new web site, also launched today, at
www.tilera.com.

Download product brief :

http://www.tilera.com/pdf/ProBrief_Tile64_Web.pdf