Toshiba has signed a license agreement for the Rambus XDR(TM) memory controller interface cell, dubbed XIO, and the Rambus PCI Express® Gen 1 PHY cell. The Rambus interface solutions will be implemented in Toshiba’s 65nm process technology for integration into the latest consumer, computing, and communications applications. The Rambus XIO memory controller is the high-performance, low-latency interface to Rambus’ XDR DRAM, today’s fastest high-speed memory. Ideal for graphics-intensive applications in consumer electronics and computing, a single, 2-byte wide, 3.2 GHz XDR DRAM component provides 6.4 GB/sec of peak bandwidth.

Rambus Inc. (Nasdaq:RMBS – News), one of the world’s premier technology
licensing companies specializing in high-speed chip interfaces, today announced
that Toshiba has signed a license agreement for the Rambus XDR(TM) memory
controller interface cell, dubbed XIO, and the Rambus PCI Express® Gen 1 PHY
cell. The Rambus interface solutions will be implemented in Toshiba’s 65nm
process technology for integration into the latest consumer, computing, and
communications applications.

"Rambus’ renowned expertise in high-speed interfaces made their solutions an
ideal choice for our state-of-art large scale integration (LSI) devices with
high processing power for various applications," said Tomotaka Saito, General
Manager of the Broadband System LSI Division at Toshiba’s Semiconductor Company.
"The addition of Rambus’ XIO and PCI Express interface cells adds to the
world-class portfolio of solutions we provide our customers."

The Rambus XIO memory controller is the high-performance, low-latency interface
to Rambus’ XDR DRAM, today’s fastest high-speed memory. Ideal for
graphics-intensive applications in consumer electronics and computing, a single,
2-byte wide, 3.2 GHz XDR DRAM component provides 6.4 GB/sec of peak bandwidth.

The advanced XDR memory architecture features four key enabling technologies
built on patented Rambus innovations:

— Differential Rambus Signaling Level (DRSL)
A low-voltage, low-power, differential signaling standard that enables scalable
multi-GHz, bi-directional, and point-to-point data busses that connect an XDR
memory controller (XIO) to XDR DRAM devices.

— Octal Data Rate (ODR)
A technology that transfers eight bits of data on each clock cycle, four times
as many as today’s state-of-the-art memory technologies that use DDR (Double
Data Rate) clocking.

— FlexPhase(TM)
A circuit technology that enables flexible phase relationships between signals,
allowing precise on-chip alignment of data with clock.

— Dynamic-Point-to-Point (DPP)
An innovation that maintains the signal integrity benefits of point-to-point
signaling on the data bus, while providing the flexibility of capacity
expansions with module upgrades. DPP was recognized with a "2005 Innovation of
the Year" award by industry publication EDN Magazine.

"Toshiba is on the forefront of delivering breakthrough solutions for
next-generation systems," said Laura Stark, senior vice president of Platform
Solutions at Rambus. "This agreement continues the long and successful
collaboration between our companies to provide state-of-the-art technology for
today’s most demanding computing and consumer electronics products."

The Rambus PCI Express PHY is one of the most widely compliance and
interoperability tested PCI Express solution available today. Rambus’
silicon-proven PCI Express PHY cells are complete serial communication cells
optimized for implementing the physical layer of the PCI Express standard.
Rambus’ PCI Express PHY cells are in production in high-volume applications and
have been incorporated in numerous products listed on the PCI-SIG® Integrators
List, having passed PCI-SIG compliance and interoperability testing by Rambus
PHY cell customers and digital controller partners. The complete, interoperable
Rambus PCI Express interface solution consists of PHY cells and digital
controllers.