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TSMC Reworking Low-K Process

In the last few months, TSMC has battled reliability issues in the back end of the line because of differences in the way low-k materials expand during thermal stress, some clients’ chips failed high-temperature tests. Low-k dielectrics deliver about a 10 percent performance improvement over fluorinated silicate glass, the more prevalent insulator. Toward the middle of last year, TSMC thought it had solved most of those issues but Newisys reopened the reliability issue at the Austin symposium. To solve the problem, TSMC went back to its library and memory compiler vendors to create redundant vias in the SRAM cells. Designers should be aware of the ongoing issues with low-k since at 90 nm since all of TSMC’s chips will be using low-k.

In the last few months, TSMC has battled reliability issues in the back end of the line because of differences in the way low-k materials expand during thermal stress, some clients’ chips failed high-temperature tests. Low-k dielectrics deliver about a 10 percent performance improvement over fluorinated silicate glass, the more prevalent insulator. Toward the middle of last year, TSMC thought it had solved most of those issues but Newisys reopened the reliability issue at the Austin symposium. To solve the problem, TSMC went back to its library and memory compiler vendors to create redundant vias in the SRAM cells. Designers should be aware of the ongoing issues with low-k since at 90 nm since all of TSMC’s chips will be using low-k.

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