Via announced plans to move into the 64-bit generation with the disclosure of its 64-bit “CN” or “Isaiah” processor. The processor would probably ship in early 2006. CN chip would be entirely compatible with previous Via processors as well as the X86-64 extensions that AMD originally designed and Intel emulated. However, the CN will be a “clean sheet” design: a fresh start. Via will likely produce multi-core “derivatives” as a complement to its single-core offerings. Via’s design constraints include dramatically improving the floating-point performance by two to three times compared to the current design. The floating-point path will be 128 bits wide. The chip will also add an additional SSE instruction, a 4x32x32 integer instruction. Adding the additional 64-bit instructions required a roughly 10-percent increase in transistor count, a satisfactory tradeoff for the additional cost. The CN will also include additional security enhancements and a larger level-2 cache as well as an embedded north bridge memory controller.

Via announced plans to move into the 64-bit generation with the disclosure of
its 64-bit "CN" or "Isaiah" processor. The processor would probably ship in
early 2006. CN chip would be entirely compatible with previous Via processors as
well as the X86-64 extensions that AMD originally designed and Intel emulated.
However, the CN will be a "clean sheet" design: a fresh start. Via will likely
produce multi-core "derivatives" as a complement to its single-core offerings.
Via’s design constraints include dramatically improving the floating-point
performance by two to three times compared to the current design. The
floating-point path will be 128 bits wide. The chip will also add an additional
SSE instruction, a 4x32x32 integer instruction. Adding the additional 64-bit
instructions required a roughly 10-percent increase in transistor count, a
satisfactory tradeoff for the additional cost. The CN will also include
additional security enhancements and a larger level-2 cache as well as an
embedded north bridge memory controller.

See also :

VIA C5J Esther
Details

VIA Next Gen "Isaiah"
CPU