VIA C5J Esther Details

  • IBM 300mm fab in East Fishkill, N.Y
  • 90nm, SOI, low-k
  • 31.7mm2
  • 26.2M transistors
  • Maximum power consumption of 3.5W at 1GHz.
  • 800MHz FSB
  • Banias bus and VIA "V4" bus
  • SSE2/SSE3 multimedia instructions
  • 128KB 32-way L2 cache
  • 2GHz and above
  • Extends the VIA PadLock Hardware Security Suite to include execution (NX)
    protection, Montgomery Multiplier support for RSA encryption and secure Hash
    (SHA-1 and SHA-256) algorithms.

The successor of Esther core, the Isaiah (CN) is expected to have smaller die
size and lower power consumption than 5W with max power draw at 1Ghz

  • IBM 300mm fab in East Fishkill, N.Y
  • 90nm, SOI, low-k
  • 31.7mm2
  • 26.2M transistors
  • Maximum power consumption of 3.5W at 1GHz.
  • 800MHz FSB
  • Banias bus and VIA "V4" bus
  • SSE2/SSE3 multimedia instructions
  • 128KB 32-way L2 cache
  • 2GHz and above
  • Extends the VIA PadLock Hardware Security Suite to include execution (NX)
    protection, Montgomery Multiplier support for RSA encryption and secure Hash
    (SHA-1 and SHA-256) algorithms.

The successor of Esther core, the Isaiah (CN) is expected to have smaller die
size and lower power consumption than 5W with max power draw at 1Ghz

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